A probabilistic model of memory acceses for efficient CPU caching [electronic resource]

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Call number	Status
3781 2016 D	In-library use

Author/Creator: Das, Subhasis.
Contributor: Dally, William J., primary advisor.; Aamodt, Tor M., advisor.; Rosenblum, Mendel, advisor.; Stanford University. Department of Electrical Engineering.

Summary: The memory hierarchy in a modern processor -- the main memory and different cache levels, consumes about half of the full system energy. We reduce the memory hierarchy energy by three methods: a) reducing main memory accesses by building better last level cache replacement policies, b) reducing wire energy in LLCs by doing intelligent placement and movement of data, and, c) reducing L1 access energy by performing accurate assignment of cache ways to memory access instructions. To design these policies, we propose a new model for program access patterns: the IID Sequence Model (ISM), which uses the reuse distance distributions of different cache lines. We show that a) our proposed Probabilistic Replacement Policy (PRP) reduces LLC misses by 6.6% over state-of-the-art replacement policies such as SHiP [91], b) Sub-Level Insertion Policy (SLIP), which places and moves cache lines according to their reuse distance distribution, reduces L2 energy by 35% and L3 energy by 22%, and, c) Cache Way Assignment (CWA) reduces L1D cache energy consumption by 14% by reducing way mispredictions.

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