Symbolic design and optimization techniques for analog integrated circuits [electronic resource]
- Siddharth Seth.
- Physical description
- 1 online resource.
All items must be viewed on site
Request items at least 2 days before you visit to allow retrieval from off-site storage. You can request at most 5 items per day.
|3781 2013 S||In-library use|
- Seth, Siddharth.
- Murmann, Boris, primary advisor.
- Horowitz, Mark Eden, advisor.
- Wooley, Bruce A., 1943- advisor.
- Stanford University. Department of Electrical Engineering.
- An analog circuit design problem typically has many acceptable solutions. However, within the very broad design space, there will usually exist one optimal design that minimizes (or maximizes) one of the objectives, given a constraint on the other metrics. The rising complexity of the circuits and the absence of closed-form expressions for certain metrics (like total integrated noise) have led to a SPICE-simulation-based numerical approach to analog circuit design and optimization, which is very slow for circuits comprising more than a handful of transistors. The research presented in this dissertation focuses on symbolic design and optimization techniques for analog integrated circuits. These techniques are based on computer optimization programs that use closed-form symbolic expressions for all relevant performance metrics of the analog circuit, bypassing the need to interface with a circuit simulator. In the first part of this work, we deal with the problem of computing total integrated noise in an analog circuit. We demonstrate a technique to compute the total integrated noise by visual inspection in linear, passive networks, and then extend the technique to show how one can symbolically integrate a general noise transfer function of any order to get closed-form expressions for total integrated noise. Such expressions were not readily available and had prevented the adoption of symbolic analysis in the design and optimization of noise limited analog circuits. Compared to previously known methods, this technique is efficient in terms of computation cycles and memory requirement, and provides the answer in a single step. We next present three proof-of-concept examples that illustrate how symbolic analysis can be applied to the design and optimization of representative analog blocks. The presented techniques are general, and taken together, can help provide a circuit designer with the best design, find sensitivities to circuit parameters, and enable rapid design portability to different sets of specification or process corners. In the first example, we present a nested-Miller-compensated three-stage operational transconductance amplifier for use in high-speed switched-capacitor circuits. Simulation results show that the 90-nm prototype amplifier achieves a 0.1 % dynamic error settling time of 2.53 ns with a total integrated noise of 240 [micro]Vrms, while consuming 5.2 mW from a 1-V power supply. In the second example, we present the design and optimization of continuous-time active-RC and gm-C low-pass filters. Starting from a given LC ladder-filter realization, we develop a systematic method of choosing the right optimization variables and using signal-flow-graph manipulations to convert a given LC ladder-filter realization into the final analog circuit. This is done in such a way that the symbolic expressions for noise, power and area turn out to be posynomial functions, enabling the formulation of the design and optimization problem as a geometric program (GP) that can be quickly solved to get the globally-optimal solution. One of the limitations in such filters is the problem of device mismatch and variability. As a solution, critical components like transconductors, resistors and capacitors are usually chosen to be integer multiples of each other. We add such practical constraints to the optimization problem, and branch-and-bound techniques are used to solve the resulting mixed-integer GP (MIGP). Finally, in the third example, we present the analysis, design, and measurement results of a low-noise, low-power, series-resonant MEMS oscillator at 20 MHz that consists of a high-Q differential resonator, wire-bonded to a high-gain CMOS transimpedance amplifier (TIA). Symbolic analysis is used to evaluate the impact of TIA bandwidth on the oscillator frequency and phase noise, and accordingly a suitable topology is chosen and optimized. Measurement results show that the designed oscillator compares favorably to the state-of-the-art in terms of its circuit design figure-of-merit.
- Publication date
- Submitted to the Department of Electrical Engineering.
- Thesis (Ph.D.)--Stanford University, 2013.
Browse related items
Start at call number: