Fixed function hardware for image processing (ISP) has been used ever since digital cameras were introduced. This solution is efficient but the resulting systems are slow to adapt because creating a new chip takes a long time. While historically this wasnt a problem, the explosion of new applications from computational photography and computer vision fields has made this approach difficult. To address the need for greater flexibility, a number of specialized accelerators were created: PVC, Hexagon, Myriad, etc. These chips rely on programmable SIMD VLIW architectures for increased flexibility. This thesis explores and evaluates an alternative approach that is more similar to traditional ISP engines - a spatially programmable architecture which is in the class of coarse-grain-reconfigurable array (CGRA) machines. We demonstrate that CGRA can be programmed as easily as a conventional CPU or GPU by using a domain specific language (DSL) for image processing like Darkroom or Hailade and leveraging an FPGA development flow based on the VPR toolset. Our evaluation framework shows that programming in space with CGRA archives a modest improvement over programming in time with SIMD: about 1.6x better energy efficiency and 1.4x better area efficiency. However the cost of programmability is still high: compared to an ASIC, CGRA has 6x worse energy and area efficiency, and this ratio would be roughly 10x if memory dominated applications were excluded. To reduce this gap requires each compute unit to do more computation making it more specialized and less flexible. How to accomplish this, while still retaining enough programmability, is the key challenge for future research.