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• Quality of Service in Information Networks.- Risk-Driven Development of Security-Critical Systems Using UMLsec.- Developing Portable Software.- Formal Reasoning About Systems, Software and Hardware.- The Problematic of Distributed Systems Supervision - An Example: GeneSyS.- Software Rejuvenation - Modeling and Analysis.- Test and Design-for-Test of Mixed-Signal Integrated Circuits.- Web Services.- Applications of Multi-Agent Systems.- Discrete Event Simulation with Application to Computer Communication Systems Performance.- Human-Centered Automation: A Matter of Agent Design and Cognitive Function Allocation.
• (source: Nielsen Book Data)

This book contains a selection of tutorials on hot topics in information technology, which were presented at the IFIP World Computer Congress. WCC2004 took place at the Centre de Congres Pierre Baudis, in Toulouse, France, from 22 to 27 August 2004. The 11 chapters included in the book were chosen from tutorials proposals submitted to WCC2004. These papers report on several important and state-of-the-art topics on information technology such as: Quality of Service in Information Networks Risk-Driven Development of Security-Critical Systems Using UMLsec Developing Portable Software Formal Reasoning About Systems, Software and Hardware Using Functionals, Predicates and Relations The Problematic of Distributed Systems Supervision Software Rejuvenation - Modeling and Analysis Test and Design-for-Test of Mixed-Signal Integrated Circuits Web Services Applications of Multi-Agent Systems Discrete Event Simulation Human-Centered Automation We hereby would like to thank IFIP and more specifically WCC2004 Tutorials Committee and the authors for their contribution. We also would like to thank the congress organizers who have done a great job. Ricardo Reis Editor QUALITY OF SERVICE IN INFORMATION NETWORKS Augusto Casaca IST/INESC, R. Alves Redol, 1000-029, Lisboa, Portugal. Abstract: This article introduces the problems concerned with the provision of end-- end quality of service in IP networks, which are the basis of information networks, describes the existing solutions for that provision and presents some of the current research items on the subject. Key words: Information networks, IP networks, Integrated Services, Differentiated Services, Multiprotocol Label Switching, UMTS.
(source: Nielsen Book Data)

As Portugal is facing strong fiscal pressure, government spending on public-private partnerships (PPPs) in the road sector has become a main budgetary constraint. In this article, we show how the financial crisis has created a unique arbitrage opportunity that provides a solution to this problem. Since the private sector is in urgent need of liquidity, we suggest that the Portuguese government should use some of the bailout funds, borrowed at lower interest rates, to buy back the roads concessions, discounting future payments at the high interest rates currently charged to Portugal. For the roads already in operation, the purchase of the assets would significantly reduce future public payments and would also release money into banks and the economy. For the roads currently under construction, we propose that the government buys only the equity of these companies. That would also reduce future payments, and allow for the postponement or even cancelation of some of these projects, while granting private companies an exit from projects that they are no longer able to finance. This operation would save around half of PPP payments over the next 20 years.

• Foreword from the Program Chair. Preface. Conference Committees. Acknowledgements. Benchmark Standards for Computing in the UK
• A. McGettrick. Student Experiments in Object-Oriented Modeling
• T. Brinda. Input/Output for CS1 Course in Java
• E.B. Koffman. Learning Programming by Solving Problems
• A.N. Kumar. Teaching of Programming with a Programmer's Theory of Programming
• J. Reinfelds. Teaching Programming Broadly and Deeply: The Kernel Language Approach
• P. Van Roy, S. Haridi. Programming Strategies using an Actor-Based Environment
• R.S. Wazlawick, A.C. Mariani. A Computing Program for Scientists and Engineers - What is The Core of Computing
• R. Denzer. Patterns of Curriculum Design
• D. Blank, D. Kumar. Variations in Computing Science's Disciplinary Diversity
• L.E. Merkle, R.E. Mercer. Variety in Views of University Curriculum Schemes for Informatics/Computing/ICT
• F. Mulder, K. Lemmen, M. van Veen. Reports of the Working Groups: Directions and Challenges in Informatics Education
• J. Hughes, A. McGettrick, E.F. Barbosa, J. Kaasboll, V.M. Kern, A.P. Ludtke Ferreira, E. Macome, J. Martins, C.A. de Oliveira, A.I. Orth, R. Sadananda, E. da Silva, R. Tori. Teaching Programming and Problem Solving
• E. Koffmann, T. Brinda, J. Alvarez, A. Kumar, M.L.B. Lisboa, J. Reinfelds, P. Van Roy, R.S. Wazlawick. Computing: The Shape of an Evolving Discipline
• L. Cassel, G. Davies, D. Kumar, R. Denzer, A. Hacquebard, R. LeBlanc, L.E. Merkle, F. Mulder, Z. Panian, R. Reis, E. Roberts, P. Rocchi, M. van Veen, A.F. Zorzo. Author Index.
• (source: Nielsen Book Data)

Several aspects of informatics curricula and teaching methods at the university level are reported in this volume, including: *Challenges in defining an international curriculum; *The diversity in informatics curricula; *Computing programs for scientists and engineers; *Patterns of curriculum design; *Student interaction; *Teaching of programming; *Peer review in education. This book contains a selection of the papers presented at the Working Conference on Informatics Curricula, Teaching Methods and Best Practice (ICTEM 2002), which was sponsored by the International Federation for Information Processing (IFIP) Working Group 3.2, and held in Florianopolis, Brazil in July 2002. The working groups were organized in three parallel tracks. Working Group 1 discussed the "Directions and Challenges in Informatics Education". The focus of Working Group 2 was "Teaching Programming and Problem Solving". Working Group 3 discussed "Computing: The Shape of an Evolving Discipline.".
(source: Nielsen Book Data)

• Chapter 1 . Introduction.- Chapter 2. Background on Soft Errors.- Chapter 3. Fault Injection Framework Using Virtual Platforms.- Chapter 4. Performance and Accuracy Assessment of Fault Injection
• Frameworks Based on VPs.- Chapter 5. Extensive Soft Error Evaluation.- Chapter 6. Machine Learning Applied to Soft Error Assessment in Multicoresystems.
• (source: Nielsen Book Data)

This book describes the benefits and drawbacks inherent in the use of virtual platforms (VPs) to perform fast and early soft error assessment of multicore systems. The authors show that VPs provide engineers with appropriate means to investigate new and more efficient fault injection and mitigation techniques. Coverage also includes the use of machine learning techniques (e.g., linear regression) to speed-up the soft error evaluation process by pinpointing parameters (e.g., architectural) with the most substantial impact on the software stack dependability. This book provides valuable information and insight through more than 3 million individual scenarios and 2 million simulation-hours. Further, this book explores machine learning techniques usage to navigate large fault injection datasets.
(source: Nielsen Book Data)

• Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.
• Use of Gray Decoding for Implementation of Symmetric Functions
• A Programmable Multi-Dimensional Analog Radial-Basis- Function-Based Classifier
• Compression-based SoC Test Infrastructures
• Parametric Structure-Preserving Model Order Reduction
• ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching
• QoS in Networks-on-Chip
• Beyond Priority and Circuit Switching Techniques
• Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis
• Statistical and Numerical Approach for a Computer efficient circuit yield analysis
• SWORD: A SAT like Prover Using Word Level Information
• A new analytical approach of the impact of jitter on continuous time delta sigma converters.
• An adaptive genetic algorithm for dynamically reconfigurable modules allocation
• The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm
• System and Procesor Design Effort Estimation
• Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors
• First Order, Quasi-Static, SOI Charge Conserving Power Dissipation Model.

International Federation for Information Processing The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of refereed international conferences in computer science and interdisciplinary fields are featured. These results often precede journal publication and represent the most current research. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing. For more information about the 300 other books in the IFIP series, please visit www.springer.com. For more information about IFIP, please visit www.ifip.org.

• Design of systems on a chip / Marcello Lubaszewski, Ricardo Reise & Jachen A.G. Jess
• Microsystems technology and applications / J. Malcolm Wilkinson
• Core architectures for digital media and the associated compilation techniques / Jachen A.G. Jess
• Past, present and future of microprocessors / Franc̦ois Anceau
• Physical design automation / Ricardo Reise, José Luís Güntzel & Marcelo Johann
• Behavioral aynthesis: an overview / Reinaldo A. Bergamaschi
• Hardware/software co-design / A. Jerraya, [et al]
• Test and design-for-test: from circuits to integrated systems / Marcello Lubaszewski
• Synthesis of FPGAs and testable ASICs / Don W. Bouldin
• Testable design and testing of microsystems / Hans G. Kerkhoff
• Embedded core-based system-on-chip test strategies / Yervant Zorian.

"Design of Systems on a Chip: Design and Test" is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular, this second book includes contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered. Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.
(source: Nielsen Book Data)

This book contains extended and revised versions of the best papers presented at the 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, held in Madrid, Spain, in September 2010. The 14 papers included in the book were carefully reviewed and selected from the 52 full papers presented at the conference. The papers cover a wide variety of excellence in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of theses systems.

This book contains extended and revised versions of the best papers presented at the 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, held in Florianópolis, Brazil, in October 2009. The 8 papers included in the book together with two keynote talks were carefully reviewed and selected from 27 papers presented at the conference. The papers cover a wide variety of excellence in VLSI technology and advanced research addressing the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of theses systems.

• Introduction, Process Variations and Flip-Flops
• Process Variability
• Flip-Flops and Hold Time Violations
• Circuits Under Test
• Measurement Circuits
• Experimental Results
• Systematic and Random Variablility
• Normality Tests
• Probability of Hold Time Violations
• Protecting Circuits Against Hold Time Violations
• Padding Efficiency Of the Proposed Padding Algorithm
• Final Remarks.

This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The consequences of variability to several aspects of circuit design, such as logic gates, storage elements, clock distribution, and any other that can be affected by process variations are discussed, with a key focus on storage elements. The authors present a statistical analysis of the critical clock skew in several test paths, due to process variability in 130nm and 90nm CMOS technology. To facilitate an on-wafer test, a measurement circuit with a precision compatible to the speed of the technology is described.

• DEDICATION. CONTRIBUTING AUTHORS. PREFACE.
• 1. INTRODUCTION.
• 2. RADIATION EFFECTS IN INTEGRATED CIRCUITS. 2.1 RADIATION ENVIROMENT OVERVIEW. 2.2 RADIATION EFFECTS IN INTEGRATED CIRCUITS. 2.2.1 SEU Classification. 2.3 PECULIAR EFFECTS IN SRAM-BASED FPGAS.
• 3. SINGLE EVENT UPSET (SEU) MITIGATION TECHNIQUES. 3.1 DESIGN-BASED TECHNIQUES. 3.1.1 Detection Techniques. 3.1.2 Mitigation Techniques. 3.1.2.1 Full Time and Hardware Redundancy. 3.1.2.2 Error Correction and Detection Codes. 3.1.2.3 Hardened Memory Cells. 3.2 EXAMPLES OF SEU MITIGATION TECHNIQUES IN ASICS. 3.3 EXAMPLES OF SEU MITIGATION TECHNIQUES IN FPGAS. 3.3.1 Antifuse based FPGAs. 3.3.2 SRAM-based FPGAs. 3.3.2.1 SEU Mitigation Solution in high-level description. 3.3.2.2 SEU Mitigation Solutions at the Architectural level. 3.3.2.3 Recovery technique.
• 4. ARCHITECTURAL SEU MITIGATION TECHNIQUES.
• 5. HIGH-LEVEL SEU MITIGATION TECHNIQUES. 5.1 TRIPLE MODULAR REDUNDANCY TECHNIQUE FOR FPGAS. 5.2 SCRUBBING.
• 6. TRIPLE MODULAR REDUNDANCY (TMR) ROBUSTNESS. 6.1 TEST DESIGN METHODOLOGY. 6.2 FAULT INJECTION IN THE FPGA BITSTREAM. 6.3 LOCATING THE UPSET IN THE DESIGN FLOORPLANNING. 6.3.1 Bit column location in the matrix. 6.3.2 Bit row location in the matrix. 6.3.3 Bit location in the CLB. 6.3.4 Bit Classification. 6.4 FAULT INJECTION RESULTS. 6.5 THE "GOLDEN" CHIP APPROACH.
• 7. DESIGNING AND TESTING A TMR MICRO-CONTROLLER. 7.1 AREA AND PERFORMANCE RESULTS. 7.2 TMR 8051 MICRO-CONTROLLER RADIATION GROUND TEST RESULTS.
• 8. REDUCING TMR OVERHEADS: PART I. 8.1 DUPLICATION WITH COMPARISON COMBINED WITH TIME REDUNDANCY. 8.2 FAULT INJECTION IN THE VHDL DESCRIPTION. 8.3 AREA AND PERFORMANCE RESULTS.
• 9. REDUCING TMR OVERHEADS: PART II. 9.1 DWC-CED TECHNIQUE IN ARITHMETIC-BASED CIRCUITS. 9.1.1 Using CED based on hardware redundancy. 9.1.2 Using CED based on time redundancy. 9.1.3 Choosing the most appropriated CED block. 9.1.3.1 Multipliers. 9.1.3.2 Arithmetic and Logic Unit (ALU). 9.1.3.3 Digital FIR Filter. 9.1.4 Fault Coverage Results. 9.1.4 Area and Performance Results. 9.2 DESIGNING DWC-CED TECHNIQUE IN NON-ARITHMETIC-BASED CIRCUITS.
• 10. FINAL REMARKS. REFERENCES.
• (source: Nielsen Book Data)

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.
(source: Nielsen Book Data)

• Chapter 1. Introduction.-
• Chapter 2. FinFET Technology.-
• Chapter 3. Reliability Challenges in FinFETs.-
• Chapter 4. Circuit-Level Mitigation Approaches.-
• Chapter 5. Evaluation Methodology.-
• Chapter 6. Process Variability Mitigation.-
• Chapter 7. Soft Error Mitigation.-
• Chapter 8. General Trade-offs.-
• Chapter 9. Final Remarks.
• (source: Nielsen Book Data)

This book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regarding the area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section.
(source: Nielsen Book Data)

This book contains extended and revised versions of the best papers presented at the 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, held in Daejeon, Korea, in October 2015. The 10 papers included in the book were carefully reviewed and selected from the 44 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about new challenges both at the physical and system-design levels, as well as in the test of these systems.

• 1- Space Radiation Environment, J.-C. Boudenot (THALES)
• 2- Radiation Effects in Microelectronics, R. Schrimpf (Vanderbilt Univ. )
• 3- In-Flight Anomalies on Electronic Devices, R. Ecoffet (CNES)
• 4- Multi-Level Fault Effects Evaluation, L. Anghel (TIMA), M. Rebaudengo, M. Sonza Reorda, M. Violante (POLI Torino)
• 5- Effects of Radiation on Analog & Mixed-Signal Circuits, M. Lubaszewski, T. Balen, E. Schuler, L.Carro (UFRGS), J.L. Huertas (IMSE-CNM)
• 6- Fundamentals of the Pulsed Laser Technique for Single-Event Upset Testing , P. Fouillat, V. Pouget (IXL), D. McMorrow (NRL). F. Darracq (IXL), S. Buchner (QSS), D. Lewis (IXL)
• 7- Design Hardening Methodologies for ASICs , F. Faccio (CERN)
• 8- Fault Tolerance in Programmable Circuits, F. Kastensmidt (UFRGS) & R. Reis (UFRGS)
• 9- Automatic Tools for Design Hardening, C. Lopez-Ongill, L. Entrena, M. Gracia-Valderas, M. Portela-Garcia (Univ. Carlos III)
• 10- Test Facilities for SEE and Dose Testing, S. Duzellier (ONERA) and G. Berger (UCL)
• 11- Error Rate Prediction of Digital Architectures: Test Methodology and Tools, R. Velazco, F, Faure (TIMA)
• 12- Using the SEEM Software for Laser SET Testing and Analysis, V. Pouget, P. Fouillat, D. Lewis (IXL).
• (source: Nielsen Book Data)

This volume provides an extensive overview of radiation effects on integrated circuits, offering major guidelines for coping with radiation effects on components. It contains a set of chapters based on the tutorials presented at the International School on Effects of Radiation on Embedded Systems for Space Applications (SERESSA) that was held in Manaus, Brazil, November 20-25, 2005.
(source: Nielsen Book Data)

• Software-Based Self-Test for Delay Faults.- On Test Generation for Microprocessors for Extended Class of Functional Faults.- Robust FinFET Schmitt Trigger Designs for Low Power Applications.- An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults.- Process Variability Impact on the SET Response of FinFET Multi-level Design.- Efficient Soft Error Vulnerability Analysis Using Non-Intrusive Fault Injection Techniques.- A Statistical Wafer Scale Error and Redundancy Analysis Simulator.- Hardware-enabled Secure Firmware Updates in Embedded Systems.- Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient Performance.- Security Aspects of Real-time MPSoCs: The Flaws and Opportunities of Preemptive NoCs.- Offset-Compensation Systems for Multi-Gbit/s Optical Receivers.- Accelerating Inference on Binary Neural Networks with Digital RRAM Processing.- Semi- and Fully-Random Access LUTs for Smooth Functions.- A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors.- Exploiting Heterogeneous Mobile Architectures through a Unified Runtime Framework.
• (source: Nielsen Book Data)

This book contains extended and revised versions of the best papers presented at the 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, held in Cusco, Peru, in October 2019. The 15 full papers included in this volume were carefully reviewed and selected from the 28 papers (out of 82 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like heterogeneous, neuromorphic and brain-inspired, biologically-inspired, approximate computing systems.
(source: Nielsen Book Data)

This book contains extended and revised versions of the best papers presented at the 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, held in Playa del Carmen, Mexico, in October 2014. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.
(source: Nielsen Book Data)