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Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits analogiques, Analog circuits, Matériel informatique, Hardware, Equipements d'entrée-sortie, Input-output equipment, Circuit analogique, Analog circuit, Circuito analógico, Circuit intégré, Integrated circuit, Circuito integrado, Circuit à signal mixte, Mixed signal circuit, Circuito de señal mixto, Espacement, Spacing, Espaciamiento, Gain, Ganancia, Routeur, Router, Signal analogique, Analog signal, Señal analógica, Solution optimale, Optimal solution, Solución óptima, Système conversationnel, Interactive system, Sistema interactivo, Système sur puce, System on a chip, Sistema sobre pastilla, Analog routing, Global routing, Interactive routing, SIAR, and Splitting graph

As analog and mixed-signal (AMS) circuitry gains increasing portions in modern SoCs, automatic analog routing is becoming more and more important. However, routing for analog circuits has always been an extremely challenging task due to complicated electrical and geometrical constraints. Due to these constraints, current analog routers often fail to obtain a routing solution that the designer wants. To incorporate the designer's expertise during routing, a customized real-time interactive analog router is attracting increasing concerns in industry. This paper presents a fast customized real-time interactive analog router called SIAR. A key feature of SIAR is that it allows for real-time interactions between the router and the designer. The designer can try different guiding points by moving the cursor in the user window and SIAR will return and display the corresponding routing solution in real-time, such that the designer could choose the most satisfactory one. The guiding points are very important for the designer to obtain satisfactory routing solutions, even for routing solutions with analog matching constraints by setting symmetric guiding points. A new splitting graph based routing model is presented to efficiently search the routing path and record the number of turns/vias during searching by efficient tile splitting operations. SIAR supports different routing modes such as point-to-point, point-to-module and module-to-module. An efficient connecting point selection method is presented such that an optimal routing solution is preserved when connecting to a module. Different design rules such as variable wire and via width/spacing rules, along with the same-net spacing rules, are supported in SIAR. Moreover, a global routing stage is presented to speedup the routing process for large designs. Experimental results are promising.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Convertisseurs de signal, Signal convertors, Circuits numériques, Digital circuits, Architecture parallèle, Parallel architectures, Canal avec bruit, Noisy channel, Canal con ruido, Canal transmission, Transmission channel, Canal transmisión, Circuit codeur, Coding circuit, Circuito codificación, Circuit décodeur, Decoding circuit, Circuito desciframiento, Codage, Coding, Codificación, Code contrôle parité, Parity check codes, Compression image, Image compression, Compresión imagen, Correction erreur, Error correction, Corrección error, Décodage, Decoding, Desciframiento, Evaluation performance, Performance evaluation, Evaluación prestación, Extensibilité, Scalability, Estensibilidad, Implémentation, Implementation, Implementación, Multimédia, Multimedia, Qualité image, Image quality, Calidad imagen, Radiocommunication, Radio communication, Radiocomunicación, Reconstruction image, Image reconstruction, Reconstrucción imagen, Réseau porte programmable, Field programmable gate array, Red puerta programable, Système n niveaux, Multilevel system, Sistema n niveles, Transmission longue distance, Long distance transmission, Transmisión larga distancia, Télécommunication sans fil, Wireless telecommunication, Telecomunicación sin hilo, Codecs, Cyclic codes, Error correction codes, and Image communication

Achieving high image quality is an important aspect in an increasing number of wireless multimedia applications. These applications require resource efficient error correction hardware to detect and correct errors introduced by the communication channel. This paper presents an innovative flexible architecture for error correction using Low-Density Parity-Check (LDPC) codes. The proposed partially-parallel decoder architecture utilizes a novel code construction technique based on multi-level Hierarchical Quasi-Cyclic (HQC) matrix. The proposed architecture is resource efficient, provides scalable throughput and requires substantially less power compared to other decoders reported to date. The proposed decoder has been implemented on a Xilinx FPGA suitable for WiMAX application and achieves a throughput of 548 Mbps. Performance evaluation of the decoder has been carried out by transmitting JPEG images over a wireless noisy channel and comparing the quality of the reconstructed images with those from other similar decoders.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Basse tension, Low voltage, Baja tensión, Circuit logique, Logic circuit, Circuito lógico, Ecart type, Standard deviation, Desviación típica, Economies d'énergie, Energy savings, Ahorros energía, Evaluation performance, Performance evaluation, Evaluación prestación, Impureté, Impurity, Impureza, Logique seuil, Threshold logic, Lógica umbral, Modélisation, Modeling, Modelización, Nanotechnologie, Nanotechnology, Nanotecnología, Porte logique, Logic gate, Puerta lógica, Processus stochastique, Stochastic process, Proceso estocástico, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Seuil tension, Voltage threshold, Umbral tensión, Temps retard, Delay time, Tiempo retardo, Transistor MOS complémentaire, Complementary MOS transistor, Transistor MOS complementario, Valeur moyenne, Mean value, Valor medio, Core speed variation, Footer transistor, Many-core, Multi-Vdd design, Multi-Vt design, Multi-core, Process variation, Process voltage and temperature variations, Random dopant fluctuation, Simulation, System level modeling, and Voltage scaling

Process variation creates core-speed discrepancy among the core in a many-core platforms. Random variation is one of the important components that contributes into core-speed discrepancy. In this paper, we propose a novel technique that uses footer transistors to reduce the impact of random process variation on delay and power in a many-core platform. Process variation is due to many fundamental deficiencies, impurities, and imperfections during the fabrication process at the nano-scale technologies. The results of this variation have a direct impact on two key parameters of the CMOS transistor: threshold voltage and gate length, which have major implication on the core speed and power. The random component of this variation is mostly attributed to the random-dopant fluctuation, which results in threshold voltage discrepancy among the cores. The proposed technique reduces the random dopant fluctuation by lowering the dopant density and then compensating the threshold voltage using a footer transistor. The results show a reduction of the total standard deviation from 25% down to 17% using the proposed method. Furthermore, the average energy saving of 30 different applications mapped on a many-core platform is improved by around 5%, and the performance by around 6%. .

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Convertisseurs de signal, Signal convertors, Algorithme, Algorithm, Algoritmo, Architecture réseau, Network architecture, Arquitectura red, Circuit intégré, Integrated circuit, Circuito integrado, Consommation électricité, Electric power consumption, Consumo electricidad, Economies d'énergie, Energy savings, Ahorros energía, Electronique faible puissance, Low-power electronics, Empilement, Stacking, Apilamiento, Energie minimale, Minimum energy, Energía mínima, Etat actuel, State of the art, Estado actual, Gestion tâche, Task scheduling, Gestión labor, Globalement asynchrone localement synchrone, Globally asynchronous locally synchronous, Globalmente asincrono localmente sincrono, Implémentation, Implementation, Implementación, Mappage, Mapping, Carta de datos, Modèle 3 dimensions, Three dimensional model, Modelo 3 dimensiones, Méthode partition, Partition method, Método partición, Optimisation, Optimization, Optimización, Partitionnement, Partitioning, Subdivisión, Processeur multicoeur, Multicore processor, Procesador MultiNúcleo, Réseau interconnexion, Interconnection network, Red interconexión, Structure 3 dimensions, Three dimensional structure, Estructura 3 dimensiones, Système sur puce, System on a chip, Sistema sobre pastilla, 3-Dimensional SoCs, Power balancing, System energy, Thermal constraint, and Voltage-frequency island

Three dimensional (3-D) multi-core SoC has been recognized as a promising solution for implementing complex applications with lower system energy. Recently, voltage-frequency island (VFI)-based design paradigm was widely adopted for energy optimization. However, the existing work commonly targeted 2-D platform, which cannot handle the exacerbated thermal issues and the increased solution space from 3-D integration. In this paper, we propose an optimization framework targeting VFI-based 3-D multi-core SoCs to minimize system energy meanwhile still meeting task deadline and thermal constraints. Our framework conducts at an earlier design phase in which designers have the freedom to determine the core stacks and map them into the hardware platform. Besides energy-aware task scheduling, we also conduct core stacking and task adjusting to balance the powers across the chip for thermal optimization. Moreover, by treating each core stack as a unity, the complicated problem of core mapping and VFI partitioning in 3-D platform can be simplified as a 2-D one. Experimental results demonstrate that on average our framework can achieve an energy reduction of 15.8% over the prior thermal balancing algorithm [17] (X. Zhou, J. Yang, Y. Xu, et al. Thermal-aware task scheduling for 3D multicore processors, IEEE Trans. Parallel Distrib. Syst. (TPDS), 21(1) (2010), 60-71.). Moreover, on average a reduction of 4.8 °C in peak temperature is achieved by our framework, compared with the state-of-the-art energy optimization scheme [8] (U.Y. Ogras, R. Marculescu, P. Choudhary, et al. Voltage-frequency island partitioning for GALS-based networks-on-chip, in: ACM/IEEE Design Automation Conference (DAC), 2007, pp. 110-115.).

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Circuit arithmétique, Arithmetic circuit, Circuito aritmético, Algorithme, Algorithm, Algoritmo, Circuit intégré, Integrated circuit, Circuito integrado, Circuit multiplicateur, Multiplying circuits, Contraste image, Image contrast, Imagen contraste, Diminution coût, Cost lowering, Reducción costes, Echelle gris, Gray scale, Escala gris, Haute fréquence, High frequency, Alta frecuencia, Implémentation, Implementation, Implementación, Logiciel, Software, Logicial, Masquage, Masking, Enmascaramiento, Qualité image, Image quality, Calidad imagen, Réseau porte programmable, Field programmable gate array, Red puerta programable, Traitement image, Image processing, Procesamiento imagen, Contrast enhancement, Logarithmic image processing, and Multiplierless log-hybrid low-complexity hardware architecture

A novel colour image enhancement architecture combining a Tonal Correction algorithm and a high frequency emphasis circular symmetric filter is implemented in hardware forming a colour image contrast enhancement system of low complexity. The architecture utilizes efficient log-domain calculations, resulting in multiplier-less operations and eliminates costly hardware division. Furthermore, the modularity of the fundamental design enables its ease of incorporation into larger and more complex designs with little modification. The design can be used for both grayscale and RGB colour images by processing each channel individually and the system can serve as a post enhancement module for improved colour rendition. The unit can be configured for the enhancement of over-exposed (too bright) and under-exposed (too dark) images based on adjustable parameters. The architecture easily fits on a basic Spartan III FPGA for low-cost realization evaluation and a Virtex 5 ML505 for real-time use. Results of the implementation and simulation are provided and compared with the software version and show that the system produces images with improved colour contrast and rendition compared to well known image enhancement algorithms such as RGB colour Homomorphic filtering. It also performs better than the Homomorphic filter and the MSRCR for faded colour images. .

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Amplificateurs, Amplifiers, Matériel informatique, Hardware, Equipements d'entrée-sortie, Input-output equipment, Amplificateur différentiel, Differential amplifier, Amplificador diferencial, Carte électronique, Printed circuit board, Tarjeta electronica, Circuit imprimé, Printed circuit, Circuito imprimido, Méthode itérative, Iterative method, Método iterativo, Plus court chemin, Shortest path, Camino más corto, Routeur, Router, Temps calcul, Computation time, Tiempo computación, Differential pair, Escape routing, and PCB design

In this paper, given a set of differential pairs (DPs) inside a single chip and the maximum tolerant length difference in a DP, a length-constrained escape routing problem in DPs is formulated. Firstly, the feasible merging connections and the feasible merging grids of all the DPs can be selected to satisfy the given length constraint and avoid routing an acute angle on a wire. Furthermore, based on the observation of the DP escape routing results from industrial boards, all the DPs can be divided into global and local DPs. By using two-phase escape routing, some local DPs can be escaped under the direction constraint and routed by using direct paths in direct escape routing and the unrouted local DPs and the global DPs can be escaped and routed by using obstacle-aware shortest paths in iterative obstacle-aware flow-based escape routing. Compared with Yan's escape router [11] and Li's escape router [12], the experimental results show that our proposed approach uses a shorter total wirelength under the larger length constraint and reduces 79.6% and 46.8% of the CPU time on the average to achieve 100% escape routability for six tested examples, respectively. Additionally, our proposed approach can obtain length- constrained escape routing results with the avoidance of routing an acute angle under the smaller length constraint for the tested example in the reasonable CPU time.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Etude théorique. Analyse et conception des circuits, Theoretical study. Circuits analysis and design, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits analogiques, Analog circuits, Circuit analogique, Analog circuit, Circuito analógico, Circuit intégré analogique, Analogue integrated circuits, Complexité calcul, Computational complexity, Complejidad computación, Conception assistée, Computer aided design, Concepción asistida, Conception circuit, Circuit design, Diseño circuito, Dimensionnement, Dimensioning, Dimensionamiento, Etat actuel, State of the art, Estado actual, Fiabilité, Reliability, Fiabilidad, Implantation circuit intégré, Integrated circuit layout, Implémentation, Implementation, Implementación, Méthode noyau, Kernel method, Método núcleo, Optimisation sous contrainte, Constrained optimization, Optimización con restricción, Programmation multiobjectif, Multiobjective programming, Programación multiobjetivo, Programme SPICE, SPICE, Propriété géométrique, Geometrical properties, Propiedad geométrica, Simulation circuit, Circuit simulation, Analog integrated circuits, Automatic module generator, Electronic design automation, Floorplan-aware circuit sizing, and Multi-objective optimization

This paper presents a methodology for analog IC circuit-level sizing and optimization, which takes into account the layout geometrical properties, by introducing a simple and general description that permits the inclusion of the floorplan generation in the sizing optimization loop with negligible computational costs. The usage of a modified NSGA-II state-of-the-art multi-objective multi-constraint optimization kernel enables the efficient exploration of design tradeoffs, while the inclusion of corner cases and the usage of the industrial circuit simulators (HSPICE® Eldo® or Spectre®) ensures the accuracy and reliability of the solutions. Several layout templates that enclose the constraints defined by the designer are used to generate multiple floorplan solutions for each sizing solution during the synthesis process, giving the optimizer pertinent and accurate geometric layout information, e.g., area, width, length, wasted area, etc. Additionally, a built-in technology independent module generator facilitates the instantiation of multiple versions of each device, further increasing the exploration of possible geometric combinations and consequently packing of the floorplan with a minimum of wasted area. The developed tool, AIDA-C, implements the proposed approach, and is validated for both classical and new analog circuit structures using the UMC 130 nm design process.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits analogiques, Analog circuits, Circuit analogique, Analog circuit, Circuito analógico, Conception circuit, Circuit design, Diseño circuito, Dimensionnement, Dimensioning, Dimensionamiento, Evaluation performance, Performance evaluation, Evaluación prestación, Linéarisation morceau, Piecewise linearization, Linearización trozo, Modélisation, Modeling, Modelización, Méthode partition, Partition method, Método partición, Optimisation, Optimization, Optimización, Partitionnement, Partitioning, Subdivisión, Propriété intellectuelle, Intellectual property, Propiedad intelectual, Référence tension, Voltage standard, Estandar voltaje, Système linéaire par morceaux, Piecewise linear system, Sistema lineal de trazos, Système n dimensions, Multidimensional system, Sistema n dimensiones, Technologie silicium sur isolant, Silicon on insulator technology, Tecnología silicio sobre aislante, Tension polarisation, Bias voltage, Voltage polarización, Analog design automation, Analog firm IP, Circuit modeling, Hierarchical sizing and biasing, Peano curves, and Simplex optimization

A fast design space exploration of analog firm intellectual properties (IP) based on Peano-like paths (piecewise linear and monodimensional) is presented. First, the n-dimensional design space is globally explored following those Peano curves, which are obtained by varying only 1 design variable at a time using a fixed step size. Each variable is taken within a given range. During exploration, the best x-percentile points are retained. After varying globally the n variables, a Nelder-Mead simplex optimization is performed using each of the best points as an initial point. Successive p-variable partitioning of the n-dimensional design space (with p ≪ n) are applied to adapt the simplex optimization to large dimensions. The proposed exploration technique is combined with a simulation-based hierarchical sizing and biasing methodology to size and bias analog firm IPs. This combined approach has been successfully applied to size and bias a Constant Voltage Reference (CVR) in a 5 V SOI 1 μm technology. The results illustrate the effectiveness and accuracy of the proposed approach.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Circuit arithmétique, Arithmetic circuit, Circuito aritmético, Circuit VLSI, VLSI circuit, Circuito VLSI, Circuit additionneur, Summing circuits, Circuit intégré, Integrated circuit, Circuito integrado, Circuit logique, Logic circuit, Circuito lógico, Conception circuit intégré, Integrated circuit design, Consommation électricité, Electric power consumption, Consumo electricidad, Diminution coût, Cost lowering, Reducción costes, Electronique faible puissance, Low-power electronics, Energie minimale, Minimum energy, Energía mínima, Etat actuel, State of the art, Estado actual, Horloge, Clock, Reloj, Logique retenue, Carry logic, Processeur 64 bits, 64 bit Processor, Procesador 64 bits, Rendement énergétique, Energetic efficiency, Rendimiento energético, Structure arborescente, Tree structure, Estructura arborescente, Temps retard, Delay time, Tiempo retardo, Adders, Hybrid adders, Low-energy, and VLSI design

An energy efficient adder design based on a hybrid carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and backwards from the MSB. The incidence at a midpoint significantly accelerates the addition. This acceleration together with combining low-cost ripple-carry and carry-chain circuits, yields energy efficiency compared to other adder architectures. The optimal midpoint is analytically formulated and its closed-form expression is derived. To avoid the quadratic RC delay growth in a long carry chain, it is optimally repeated. The adder is enhanced in a tree-like structure for further acceleration. 32, 64 and 128-bit adders targeting 500 MHz and 1 GHz clock frequencies were designed in 65 nm technology. They consumed 11-18% less energy compared to adders generated by state-of-the-art EDA synthesis tool.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Convertisseurs de signal, Signal convertors, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Electronique de puissance, alimentations électriques, Power electronics, power supplies, Agrégation, Aggregation, Agregación, Algorithme récursif, Recursive algorithm, Algoritmo recursivo, Alimentation à commutation, Switching power supply, Alimentación con conmutación, Alimentation électrique, Power supply, Alimentación eléctrica, Circuit puissance, Power circuit, Circuito potencia, Classification automatique, Automatic classification, Clasificación automática, Complexité calcul, Computational complexity, Complejidad computación, Conception conjointe, Codesign, Diseño conjunto, Consommation électricité, Electric power consumption, Consumo electricidad, Convertisseur puissance, Power converter, Convertidor potencia, Electronique faible puissance, Low-power electronics, Electronique puissance, Power electronics, Electrónica potencia, Energie minimale, Minimum energy, Energía mínima, Evaluation performance, Performance evaluation, Evaluación prestación, Réseau électrique, Electrical network, Red eléctrica, Système temps réel, Real time system, Sistema tiempo real, Temps exécution, Execution time, Tiempo ejecución, LDO, On-chip power delivery, Power supply co-design, and SMPS

Efficient on-chip power delivery is a significant design challenge in heterogeneous real time systems with multiple power domains. The power efficiency of the overall heterogeneous power delivery system has recently been shown to be a strong function of the clustering of the power supplies - the specific configuration in which the power converters and regulators are co-designed. A recursive clustering algorithm with polynomial computational complexity is proposed for a dynamically controllable power distribution system. The algorithm is evaluated on IBM power grid benchmark circuits, yielding up to a 21% increase in power efficiency, and orders of magnitude speedup in runtime.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Autres dispositifs multijonctions. Transistors de puissance. Thyristors, Other multijunction devices. Power transistors. Thyristors, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Algorithme, Algorithm, Algoritmo, Capacité électrique, Capacitance, Capacitancia, Caractéristique électrique, Electrical characteristic, Característica eléctrica, Circuit intégré CMOS, CMOS integrated circuits, Circuit intégré, Integrated circuit, Circuito integrado, Circuit logique, Logic circuit, Circuito lógico, Circuit numérique, Digital circuit, Circuito numérico, Conception circuit, Circuit design, Diseño circuito, Conception optimale, Optimal design, Concepción optimal, Consommation électricité, Electric power consumption, Consumo electricidad, Critère conception, Design criterion, Criterio concepción, Electronique puissance, Power electronics, Electrónica potencia, Evaluation performance, Performance evaluation, Evaluación prestación, Extensibilité, Scalability, Estensibilidad, Extraction paramètre, Parameter extraction, Extracción parámetro, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Fiabilité, Reliability, Fiabilidad, Interconnexion, Interconnection, Interconexión, Lithographie, Lithography, Litografía, Logique seuil, Threshold logic, Lógica umbral, Porte logique, Logic gate, Puerta lógica, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Seuil tension, Voltage threshold, Umbral tensión, Simulation numérique, Numerical simulation, Simulación numérica, Temps retard, Delay time, Tiempo retardo, Transistor puissance, Power transistor, Transistor potencia, Asynchronous router, Die-to-die variation, Environment variation, ISCAS85, Variation-aware methodology, and Within-die variation

In submicron technology, during the fabrication process factors like lithography and lens defect can change some of the physical parameters of transistors and interconnects. This change can modify the transistor electrical characteristics such as current, threshold voltage and gate capacitance, and thus it causes variation in power, delay and performance of the circuit. Process variation has become one of designer's challenges to the point that in below 45 nm technology it is considered as the most important issue in reliability. Power consumption and transistors variation are limiting factors to physical scalability. In this paper, we propose two approaches to reduce D2D and WID variations effects on digital CMOS circuits, at design time. The first approach concerns a variation-aware algorithm capable of extracting optimal design parameters to decrease variation and power. The second approach, using transistor stacking will help further reduce variation and power. Applying the algorithm on a digital design and according to parameters behavior in the presence of variation, we extract for each parameter value that will lead to power and variation reduction. On the other hand, with the stacking approach only basic gates are considered and subsequently gate configurations that reduce power and variation are proposed. The proposed approaches could be used identically for synchronous and asynchronous circuits. To prove this claim, we apply our approaches to a network-on-chip asynchronous router and a circuit from the ISCAS85 benchmark. All simulations are done in 32 nm technology using the HSPICE tool. The proposed algorithm similar to Monte Carlo simulation achieves the same results; however with lower execution time. The application of stacking approach to both asynchronous router and ISCAS85 circuit reduces variation effects up to 40.9% and 13.35%, respectively.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Circuit séquentiel, Sequential circuit, Circuito secuencial, Circuit bistable, Flip-flop circuits, Circuit intégré, Integrated circuit, Circuito integrado, Consommation électricité, Electric power consumption, Consumo electricidad, Diaphonie, Crosstalk, Diafonía, Economies d'énergie, Energy savings, Ahorros energía, Electronique faible puissance, Low-power electronics, Gain, Ganancia, Horloge, Clock, Reloj, Interconnexion, Interconnection, Interconexión, Optimisation, Optimization, Optimización, Multi-bit flip-flop, Physical design, Power optimization, and Synthesis for low power

Applying multi-bit flip-flops (MBFFs) for clock power reduction in modern nanometer ICs has been becoming a promising lower-power design technique. Many previous works tried to utilize as more MBFFs with larger number of bits as possible to gain more clock power saving. However, an MBFF with larger number of bits may lead to serious crosstalk due to the close interconnecting wires belonging to different signal nets which are connected to the same MBFF. This paper analyzes, evaluates, and compares the relationship between power consumption and crosstalk when applying MBFFs with different numbers of bits. To solve the addressed problem, a novel crosstalk-aware power optimization approach is further proposed to optimize power consumption while satisfying the crosstalk constraint. Experimental results show that the proposed approach is very effective in crosstalk avoidance when applying MBFFs for power optimization.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Filtres de fréquence, Frequency filters, Circuits numériques, Digital circuits, Banc filtre, Filter bank, Banco filtro, Circuit additionneur, Summing circuits, Circuit intégré, Integrated circuit, Circuito integrado, Circuit multiplicateur, Multiplying circuits, Conception compacte, Compact design, Concepción compacta, Consommation électricité, Electric power consumption, Consumo electricidad, Correction optique de proximité, Optical proximity correction, Corrección de proximidad óptica, Electronique faible puissance, Low-power electronics, Energie minimale, Minimum energy, Energía mínima, Evaluation performance, Performance evaluation, Evaluación prestación, Filtre numérique, Digital filter, Filtro numérico, Filtre retard, Delay filters, Filtre réponse impulsion finie, Finite impulse response filter, Filtro respuesta impulsión acabada, Implémentation, Implementation, Implementación, Montage cascade, Cascade connection, Conexión cascada, Parallélisme, Parallelism, Paralelismo, Phase linéaire, Linear phase, Fase lineal, Processeur 16 bits, 16 bit Processor, Procesador 16 bits, Précision élevée, High precision, Precisión elevada, Rapport signal bruit, Signal to noise ratio, Relación señal ruido, Silicium, Silicon, Silicio, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Virgule flottante, Floating point, Coma flotante, ANSI S1.11 1/3-octave filter bank, Cascaded datapath, Hearing aid, Linear-phase FIR filter, and Static floating-point arithmetic

The main contribution of this study is the development of an area-/energy-efficient cascaded direct-truncation (DT) datapath with the so-called static floating-point (SFP) arithmetic to realize a low-delay analysis filter bank (AFB) for digital hearing aids. In the proposed SFP LPFIR (linear-phase finite impulse response) filter engine, lower silicon area and lesser power consumption facilitate better SNR performance than that achieved with the conventional post-truncation (PT) datapath with integer arithmetic. Moreover, in the proposed LPFIR filter engine, a cascaded 16-bit SFP A-M-S-Acc datapath is used that consists of two embedded 1-bit shifters to improve hardware usage and parallelism, one 16-bit DT adder (A), one 16-bit DT multiplier (M), one 16-bit barrel shifter (S), and one 16-bit DT accumulator (Acc). The operations per cycle (OPC) of the proposed SFP LPFIR filter engine reaches 6, which enables efficient fabrication of the low-latency AFB for hearing aids. To verify the effectiveness of the proposed 16-bit SFP LPFIR filter engine, a 10-ms 18-band quasi-ANSI S1.11 1/3-octave AFB for digital hearing aids was implemented using UMC 90-nm CMOS technology. The AFB was operated at 792 kHz to process, in real-time, 24 kHz audio, with the power consumption being approximately 80.6 μW (at 1 V). Compared to the previous design in which the conventional PT datapath with integer arithmetic was used, approximately 9.6% of total power and 8.3% of silicon area were saved and almost the same SNR (signal-to-noise ratio) performance was achieved with the new system, when evaluated by a 3.96-s sequence of Mandarin speech.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Oscillateurs, résonateurs, synthétiseurs, Oscillators, resonators, synthetizers, Convertisseurs de signal, Signal convertors, Circuits de conditionnement de caractéristiques des signaux (incluant les circuits à retard), Circuits of signal characteristics conditioning (including delay circuits), Circuits numériques, Digital circuits, Convertisseur fréquence, Frequency converter, Convertidor frecuencia, Boucle verrouillage phase, Phase locked loop, Bucle enclavamiento fase, Bruit phase, Phase noise, Ruido fase, Circuit numérique, Digital circuit, Circuito numérico, Commande numérique, Digital control, Mando numérico, Conception circuit, Circuit design, Diseño circuito, Critère conception, Design criterion, Criterio concepción, Diviseur fréquence, Frequency divider, Divisor frecuencia, Détecteur phase, Phase detector, Detector fase, Modélisation, Modeling, Modelización, Méthode analytique, Analytical method, Método analítico, Oscillateur, Oscillator, Oscilador, Source bruit, Noise source, Fuente ruido, ADPLL, Digitally controlled oscillator, Fractional-N PLL, Phase-frequency detector, and Spur

This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, fractional spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur. Applying the proposed noise model, circuit variables in ADPLL can be properly selected to meet phase noise, fractional spur and locking time requirements. For model validation, we collect ADPLL circuit designs published in recent literatures and perform model analysis. The analysis results and hardware measurements obtain good agreements.

Electronics, Electronique, Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Circuits hyperfréquences, circuits intégrés hyperfréquences, lignes de transmission hyperfréquences, circuits à ondes submillimétriques, Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits, Telecommunications et theorie de l'information, Telecommunications and information theory, Télécommunications, Telecommunications, Radiocommunications, Antennes, Antennas, Alliage semiconducteur, Semiconductor alloys, Alliage Ge Si, Ge-Si alloys, Antenne intégrée, Integrated antenna, Antena integrada, Antenne microruban, Microstrip antennas, Antenne réflecteur, Reflector antenna, Antena reflector, Antenne réseau équiphase, Phased array antenna, Antena red equifase, Circuit MMIC, MMIC, Circuit actif, Active circuit, Circuito activo, Circuit combinateur, Combiner circuit, Circuito combinador, Circuit commande, Control circuit, Circuito control, Circuit intégré, Integrated circuit, Circuito integrado, Circuit numérique, Digital circuit, Circuito numérico, Combinateur puissance, Power combiners, Commande numérique, Digital control, Mando numérico, Distribution puissance, Power distribution, Evaluation performance, Performance evaluation, Evaluación prestación, Interconnexion, Interconnection, Interconexión, Multicouche, Multiple layer, Capa múltiple, Technologie planaire, Planar technology, Tecnología planar, Réseau d'antennes, and Antenna array

A highly integrated phased array transmit/receive architecture is presented. Multilayer microstrip antennas with a scanning potential up to 60° are combined, on a common manifold, with SiGe MMICs including four RF channels each, together with the necessary digital control circuits. Power distribution and combining are realised by the concept of a folded planar reflectarray. This study also includes the necessary solutions for multilayer interconnects and efficient heat removal from the active circuits. To prove the concept, passive arrays with different fixed beam positions have been tested successfully; followed by a first active array demonstrating excellent scanning performance up to 60° both in E- and H-plane.

Electronics, Electronique, Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits hyperfréquences, circuits intégrés hyperfréquences, lignes de transmission hyperfréquences, circuits à ondes submillimétriques, Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits, Hyperfréquence, Microwave, Hiperfrecuencia, Actionneur piézoélectrique, Piezoelectric actuators, Bande fréquence, Frequency band, Banda frecuencia, Cavité, Cavity, Cavidad, Circuit accordable, Tunable circuit, Circuito acordable, Circuit imprimé, Printed circuit, Circuito imprimido, Dispositif piézoélectrique, Piezoelectric device, Dispositivo piezoeléctrico, Electromagnétisme, Electromagnetism, Electromagnetismo, Evaluation performance, Performance evaluation, Evaluación prestación, Impédance, Impedance, Impedancia, Logiciel, Software, Logicial, Modèle 2 dimensions, Two dimensional model, Modelo 2 dimensiones, Modèle 3 dimensions, Three dimensional model, Modelo 3 dimensiones, Onde millimétrique, Millimetric wave, Onda milimétrica, Onde plane, Plane wave, Onda plana, Prototype, Prototipo, Simulation, Simulación, Structure plane, Plane structure, Estructura plana, Substrat diélectrique, Dielectric substrate, Substrato dieléctrico, Plan de masse, Ground plane, Surface déphasante, and Phase-shifting surface

A novel technique for tuning periodic phase shifting surfaces at millimetre-waves is presented. The proposed structure consists of a periodic surface placed over a ground plane creating an air cavity. The periodic surface is formed by a two-dimensional array of metallic square loop elements printed on a 0.8 mm thick dielectric substrate. When excited by a plane wave, the structure is acting as an artificial impedance surface, reflecting the incident wave with a wide range of phase values within a specific frequency band. The tuning is achieved by means of a small number of piezoelectric actuators which support the periodic surface. The actuators are placed around the periodic surfaces thereby not interfering with the radiation performance and introducing no losses. They produce a displacement between the periodic surface and the ground plane when voltage is applied, which in turn changes the reflection phase response of the structure. Full wave periodic simulations have been carried out in three-dimensional electromagnetic simulation software (CST Microwave Studio™) to extract the reflection characteristics and evaluate the expected tuning range of the proposed structure. A prototype has been fabricated and measured validating the concept.

Electronics, Electronique, Optics, Optique, Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Oscillateurs, résonateurs, synthétiseurs, Oscillators, resonators, synthetizers, Amplificateurs, Amplifiers, Convertisseurs de signal, Signal convertors, Telecommunications et theorie de l'information, Telecommunications and information theory, Télécommunications, Telecommunications, Radiocommunications, Emetteurs. Récepteurs, Transmitters. Receivers, Adaptabilité, Adaptability, Adaptabilidad, Amplificateur, Amplifier, Amplificador, Charge électroénergétique, Power system load, Carga electroenergética, Circuit 2 accès, Two-port networks, Commutation, Switching, Conmutación, Conception circuit, Circuit design, Diseño circuito, Convertisseur courant continu, Direct current convertor, Convertidor corriente continua, Convertisseur impédance, Impedance converter, Convertidor impedancia, Diode barrière Schottky, Schottky barrier diode, Diodo barrera Schottky, Electronique puissance, Power electronics, Electrónica potencia, Emetteur, Transmitter, Emisor, Evaluation performance, Performance evaluation, Evaluación prestación, Impédance charge, Load impedance, Impedancia carga, Miniaturisation, Miniaturization, Miniaturización, Optimisation, Optimization, Optimización, Problème non linéaire, Nonlinear problems, Redresseur, Rectifier, Rectificador, Récepteur, Receiver, Receptor, Résonateur, Resonator, Resonador, Sous système, Subsystem, Subsistema, Transistor effet champ, Field effect transistor, Transistor efecto campo, Transistor puissance, Power transistor, Transistor potencia, Electricité sans fil, Wireless electricity, AlGaN/GaN HEMT, class-D amplifier, inductive resonant (IR) link, and wireless power transfer (WPT)

In this paper, we describe a rigorous theoretical approach to the circuit-level nonlinear design of an entire inductive resonant wireless power transfer (IR-WPT) system, including the transmitter and receiver nonlinear subsystems. Starting from a novel analytical characterization of the inductive resonant link, the system efficiency is parametrically computed as a function of a set of circuital parameters, including the power levels to be transferred. These quantities are then used as design goals inside the nonlinear optimization of the transmitter and receiver blocks. By adopting the last generation miniaturized enhanced-mode AlGaN/GaN-power field-effect transistor and fast Schottky diodes, a Class-D amplifier and a full-bridge rectifier followed by a switching dc-dc Buck converter that acts as load impedance transformer are designed in a single optimization process at 6.78 MHz. Thus, the transmitter and the receiver are directly connected by the IR two-port network, and the system is capable to adapt to variable distances between the resonators of the IR-WPT link. The choice of the Class-D topology for the transmitter and the adaptability of the active receiver enable to get rid of inter-stage matching networks, which can severely reduce the overall efficiency, especially in high power transfer environments. With the proposed IR-WPT system, up to 44 W of transferred power and a peak of 73% dc-to-dc efficiency were obtained with an input dc voltage VDC = 30 V at a link distance D = 5 cm. Numerical and experimental results are discussed, demonstrating the accuracy of the proposed design procedure.