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Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Diminution coût, Cost lowering, Reducción costes, Estimateur, Estimator, Estimador, Estimation paramètre, Parameter estimation, Estimación parámetro, Matrice formage, Die, Matriz formadora, Méthode Monte Carlo, Monte Carlo method, Método Monte Carlo, Méthode statistique, Statistical method, Método estadístico, Simulation numérique, Numerical simulation, Simulación numérica, Système intelligent, Intelligent system, Sistema inteligente, Temps retard, Delay time, Tiempo retardo, Transistor, Logical effort, Monte Carlo, Statistical timing analysis, and Timing yield estimation

Considerable effort has been expended in the EDA community during the past decade in trying to cope with the so-called statistical timing problem. In this paper, we not only present a fast and approximate gate delay model called stochastic logical effort (SLE) to capture the effect of statistical parameter variations on the delay but also combine this model with a previously proposed transistor level smart Monte Carlo method to construct ISLE timing yield estimator. The results demonstrate that our approximate SLE model can capture the delay variations and ISLE achieves the same accuracy as the standard Monte Carlo estimator with a cost reduction of about 180 x on the average for ISCAS'85 benchmark circuits and in the existence of both inter- and intra-die variations.

Electrical engineering, Electrotechnique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Matériaux, Materials, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Electroénergétique, Electrical power engineering, Réseaux et lignes électriques, Power networks and lines, Divers, Miscellaneous, Choix matériau, Material selection, Selección material, Cycle thermique, Thermal cycle, Ciclo térmico, Dispositif semiconducteur, Semiconductor device, Dispositivo semiconductor, Electronique puissance, Power electronics, Electrónica potencia, Environnement hostile, Hostile environment, Medio ambiente hóstil, Essai cisaillement, Shear test, Ensayo cortante, Essai thermique, Thermal test, Prueba térmica, Etat surface, Surface conditions, Estado superficie, Etude comparative, Comparative study, Estudio comparativo, Evaluation performance, Performance evaluation, Evaluación prestación, Frittage, Sintering, Sinterización, Haute température, High temperature, Alta temperatura, Matrice formage, Die, Matriz formadora, Microassemblage, Microassembling, Micromontaje, Microscopie acoustique, Acoustic microscopy, Microscopía acústica, Nanoparticule, Nanoparticle, Nanopartícula, Packaging électronique, Electronic packaging, Packaging electrónico, Point fusion, Melting point, Punto fusión, Produit nouveau, New product, Producto nuevo, Propriété thermomécanique, Thermomechanical properties, Propriedad termomecánica, Réseau électrique, Electrical network, Red eléctrica, Semiconducteur bande interdite large, Wide band gap semiconductors, Substrat semiconducteur, Semiconductor substrate, Substrato semiconductor, Die-attach, harsh environment applications, nanoparticles Ag sintering, power devices packaging, and thermomechanical degradation

Currently, the demand by new application scenarios of increasing operating device temperatures in power systems is requiring new die-attach materials with higher melting points and suitable thermomechanical properties. This makes the die-attach material selection, die-attaching process, and thermomechanical evaluation a real challenge in nowadays power packaging technology. This paper presents a comparative analysis of the thermomechanical performance of high-temperature die-attach materials (sintered nano-Ag, AuGe, and PbSnAg) under harsh thermal cycling tests. This study is carried out using a test vehicle formed by four dice (considering Si and SiC semiconductors) and Cu substrates. Thermally cycled test vehicles have been thermomechanically evaluated using die-shear tests and acoustic microscopy inspections. Besides, special attention is paid to set up a nano-Ag sintering process, in which the effects of sintering pressure or substrate surface state (roughness and surface activation) on the die-attach layer are analyzed. As a main result, this study shows that the best die-attach adherence is obtained for nano-Ag when pressure is applied on the dice (using a specifically designed press) during the sintering process (11 MPa provided die-shear forces of 53 kgf). However, this die-attach presents a faster thermomechanical degradation under harsh thermal cycling tests than other considered high-temperature die-attach materials (AuGe and PbSnAg) and PbSnAg shows the best thermomechanical performances.

Electrical engineering, Electrotechnique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Diodes, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Convertisseurs de signal, Signal convertors, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Machines électriques, Electrical machines, Convertisseurs, Convertors, Commutation, Switching, Conmutación, Convertisseur tension, Voltage converter, Convertidor voltaje, Diode couche intrinsèque, p i n diode, Diodo capa intrínseca, Etude comparative, Comparative study, Estudio comparativo, Evaluation performance, Performance evaluation, Evaluación prestación, Fluctuation température, Temperature fluctuation, Fluctuación temperatura, Matrice formage, Die, Matriz formadora, Moyenne tension, Medium voltage, Tensión media, Oscillation, Oscilación, Perte commutation, Switching loss, Pérdida conmutación, Puissance sortie, Output power, Potencia salida, Comparison, NPC, SiC diode, device characterization, and medium voltage converter

This paper introduces a 6.5-kV 1-kA SiC PiN diode module for megawatt-range medium voltage converters. The analysis comprises a short description of the die and module technology and a device characterization. The effects of di/dt and temperature variation, as well as parasitic oscillations are discussed. A comparison of the results with a commercial Si diode (6.5 kV and 1.2 kA) is included. In the last section, an estimation of maximum converter output power, maximum switching frequency, losses and efficiency in a 3L-NPC converter operating with SiC and Si diodes is presented. The analyzed diode module exhibits a very good performance regarding switching loss reduction, which allows an increase of at least 16% in the output power of a 6-MVA converter. Alternatively, the switching frequency can be increased by 46%.

Electronics, Electronique, Optics, Optique, Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits hyperfréquences, circuits intégrés hyperfréquences, lignes de transmission hyperfréquences, circuits à ondes submillimétriques, Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits, Telecommunications et theorie de l'information, Telecommunications and information theory, Télécommunications, Telecommunications, Radiocommunications, Propagation des ondes radioélectriques, Radiowave propagation, Diffraction, diffusion, réflexion, Diffraction, scattering, reflection, Radiorepérage et radionavigation, Radiolocalization and radionavigation, Capacité parasite, Spurious capacity, Capacidad parásita, Conversion énergie, Energy conversion, Conversión energética, Courant fuite, Leakage current, Corriente escape, Câblage, Wiring, Colocación cables, Dimensionnement, Dimensioning, Dimensionamiento, Evaluation performance, Performance evaluation, Evaluación prestación, Faisabilité, Feasibility, Practicabilidad, Implémentation, Implementation, Implementación, Large bande, Wide band, Banda ancha, Lecteur, Reader, Lector, Matrice formage, Die, Matriz formadora, Onde décimétrique, UHF wave, Onda decimétrica, Onde millimétrique, Millimetric wave, Onda milimétrica, Optimisation, Optimization, Optimización, Redresseur, Rectifier, Rectificador, Routage, Routing, Enrutamiento, Système interconnecté, Interconnected system, Sistema interconectado, Taux conversion, Conversion rate, Factor conversión, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Transistor MOS, MOS transistor, Transmission haut débit, High rate transmission, Transmisión alta caudal, Electricité sans fil, Wireless electricity, Active RF identification (RFID), CMOS, backscattering, batteryless, millimeter wave, millimeter-wave identification (MMID), passive RFID, power conversion efficiency (PCE), rectifier, ultra-high frequency (UHF), and wireless power transmission

This paper presents the development and demonstration of a high-efficiency rectifier for millimeter-wave-to-dc energy conversion. It is a critical circuit block that renders possible the use of a single CMOS chip die with no substrate and wiring, as the implementation of a batteryless, yet active tag for next-generation high data-rate millimeter-wave identification technologies. We also propose an architecture of a reader-tag system that addresses the underlying technical challenges. The rectifier is based on a differential drive cross-coupled topology that has been shown to work at UHF frequencies only so far. In this paper, we investigate significant challenges in implementing this topology at millimeter-wave frequencies with good power conversion efficiency (PCE). The analyses, design, and results presented in this work demonstrate the feasibility of achieving this by minimizing simultaneously the small on-resistance and the reverse leakage current in the MOS transistors, and by reducing losses and parasitic capacitances through proper transistor sizing and layout optimization. Using a standard 65-nm bulk CMOS process, a chip was designed, fabricated, and tested under different input and output loading conditions. The rectifier exhibits an overall PCE of 20% at 24 GHz, 18% at 35 GHz, and 11% at 60 GHz under RF available driving power of 6, 6, and 3 dBm, respectively, and output load resistance of 1, 1, and 2 kΩ, respectively. These PCE performances at millimeter-wave frequencies have never been reported in the literature.

Electrical engineering, Electrotechnique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Matériel électrique divers, Various equipment and components, Isolateurs, Insulators, Electronique de puissance, alimentations électriques, Power electronics, power supplies, Appareillage essai, Testing equipment, Aparato ensayo, Borne supérieure, Upper bound, Cota superior, Caractéristique électrique, Electrical characteristic, Característica eléctrica, Dispositif puissance, Power device, Dispositivo potencia, Diélectrique, Dielectric materials, Dieléctrico, Elastomère, Elastomer, Elastómero, Electronique haute température, High-temperature electronics, Electronique puissance, Power electronics, Electrónica potencia, Encapsulation, Encapsulación, Fissuration, Cracking, Agrietamiento, Fissure, Crack, Fisura, Grande puissance, High power, Gran potencia, Haute température, High temperature, Alta temperatura, Haute tension, High voltage, Alta tensión, Isolateur, Insulator, Aislador, Matrice formage, Die, Matriz formadora, Packaging électronique, Electronic packaging, Packaging electrónico, Propriété diélectrique, Dielectric properties, Propiedad dieléctrica, Puissance volumique, Power density, Semiconducteur, Semiconductor materials, Semiconductor(material), Silicium, Silicon, Silicio, Structure sandwich, Sandwich structure, Estructura sandwich, Température ambiante, Room temperature, Temperatura ambiente, Vieillissement thermique, Thermal ageing, Envejecimiento térmico, Dielectric measurements, elastomer, encapsulation, packaging, power semiconductor devices, and silicone gel

High-temperature power electronics represent an increasing demand. Higher power density or severe ambient temperature applications become the trend, while silicon carbide components with 250―300 °C Tjm ax are emerging. Among materials used in high-voltage power module, soft encapsulants play a significant role in improving both semiconductor die and module package voltage ratings, especially under enhanced electrical and thermal constraints. In operation close to their upper temperature limit, two silicone materials were selected among the most thermally stable soft insulators available today. Up to 300 °C, dielectric properties and their stability under isothermal aging in air ambient tests were characterized. The gel, tested using sandwich structures, exhibits cracking of its exposed-to-air face, at an aging temperature as low as 250 °C after less than 100 h. The elastomer, tested as free films, presents no cracking, no degraded electrical characteristics, and a 6 % relative mass loss, after 500 h aging. Moreover, the elastomer insulating properties, at low and high electric field, remains stable up to 300 °C (short-term tests), contrary to the gel which shows a strong increase in dc electrical conductivity. So the elastomer shows promising properties for improved encapsulation performance at 250 °C, to be further investigated in package configurations.

Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Intelligence artificielle, Artificial intelligence, Metaux. Metallurgie, Metals. Metallurgy, Transformation de matériaux métalliques, Production techniques, Formage, Forming, Emboutissage, Deep drawing, Formage à la presse des métaux en feuille et en fils, Press forming of metal foils and wires, Genie mecanique. Construction mecanique, Mechanical engineering. Machine design, Généralités, General, Automatisation, Automation, Automatización, Automatisierung, Base de connaissances, Knowledge base, Base conocimiento, Choix procédé, Process selection, Selección proceso, Verfahrenswahl, Conception assistée, Computer aided design, Concepción asistida, Conception ingénierie, Engineering design, Concepción ingeniería, Condition opératoire, Operating conditions, Condición operatoria, Coût, Costs, Coste, Kosten, Emboutissage, Deep drawing, Estampado, Tiefziehen, Formage, Forming, Conformado, Umformen, Injection vapeur, Steam injection, Inyección vapor, Matrice emboutissage, Deep drawing die, Matriz embutición, Ziehform, Matrice formage, Die, Matriz formadora, Matrize, Modélisation, Modeling, Modelización, Problème découpe, Cutting stock problem, Problema troquelado, Processus conception, Design process, Proceso concepcion, Rendement matière, Yield(material economy), Rendimiento materia, Ausbringen, Règle production, Production rule, Regla producción, Système expert, Expert system, Sistema experto, Expertensystem, Système modulaire, Modular system, Sistema modular, Tôle, Sheet metal, Chapa, Blech, AutoCAD, expert system, process parameters, production rule, progressive deep drawing die, sheet metal industries, and strip-layout design

The selection of process parameters and strip-layout design are important activities in sheet metal industries for production of deep drawn sheet metal parts. Traditionally, these are manual, tedious, time consuming and highly experience-based tasks. In the present work, an expert system (ES) is developed for automation of these activities for production of sheet metal parts on progressive deep drawing die. Production rule-based approach is used for constructing system modules. The proposed system automates the selection of appropriate values of process parameters and design of strip-layout for production of deep drawn parts on progressive deep drawing die. The system is also capable to model blank layout and strip-layout automatically in the drawing editor of AutoCAD. The system has been tested successfully for wide variety of industrial deep drawn parts. The system can be easily implemented on a PC having AutoCAD software; therefore it has low cost of implementation.

Electrical engineering, Electrotechnique, Physics, Physique, Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Electronique de puissance, alimentations électriques, Power electronics, power supplies, Terre, ocean, espace, Earth, ocean, space, Sciences de la terre, Earth sciences, Géophysique interne, Internal geophysics, Séismes, sismologie, Earthquakes, seismology, Geophysique externe, External geophysics, Météorologie, Meteorology, Analyse et prévision du temps, Weather analysis and prediction, Alimentation électrique, Power supply, Alimentación eléctrica, Capacité électrique, Capacitance, Capacitancia, Carte électronique, Printed circuit board, Tarjeta electronica, Cavité, Cavity, Cavidad, Circuit imprimé, Printed circuit, Circuito imprimido, Circuit intégré, Integrated circuit, Circuito integrado, Commutation, Switching, Conmutación, Electronique puissance, Power electronics, Electrónica potencia, Gigue, Jitter, Fluctuación, Haute fréquence, high frequency, Horloge, Clock, Reloj, Implémentation, Implementation, Implementación, Impédance, impedance, Inductance, Inductancia, Intervalle temps, Time interval, Intervalo tiempo, Logique temporelle, Temporal logic, Lógica temporal, Matrice formage, Die, Matriz formadora, Méthode domaine temps fréquence, Time frequency domain method, Método dominio tiempo frecuencia, Méthode domaine temps, Time domain method, Método dominio tiempo, Packaging électronique, Electronic packaging, Packaging electrónico, Réseau porte programmable, Field programmable gate array, Red puerta programable, Réseau électrique, Electrical network, Red eléctrica, Simulation système, System simulation, Simulación sistema, 0540C, 0750H, 4727S, 8430J, 9130P, 9260W, Impedance, integrated circuit (IC), modeling, noise, power delivery network (PDN), and power integrity

Switching current drawn by an integrated circuit (IC) creates dynamic power supply noise on the IC and on the printed circuit board (PCB), which in turn causes jitter in I/O signals and reduces the maximum clock frequency. Predicting power supply noise is challenging due to the complexity of determining the dynamic current drawn by the IC and the impedance of the power delivery network. In this paper, a methodology is developed for predicting dynamic power supply noise on the PCB resulting from logic activity in a field-programmable gate array (FPGA). Time-domain switching currents within the FPGA are found by performing power simulations of the implemented logic over small time intervals. A high-frequency model of the die―package―PCB power delivery network is developed based on the inductance and capacitance of the package and die and a cavity model description of the PCB. The technique is shown to accurately predict noise on the PCB in both the time and frequency domains.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Essais, mesure, bruit et fiabilité, Testing, measurement, noise and reliability, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Metaux. Metallurgie, Metals. Metallurgy, Transformation de matériaux métalliques, Production techniques, Traitements thermiques, Heat treatment, Recuit, Annealing, Contrôle, Analysing. Testing. Standards, Contrôle non destructif, Nondestructive testing, Circuit intégré, Integrated circuit, Circuito integrado, Integrierte Schaltung, Contrainte déformation, Stress strain, Tensión deformante, Contrainte mécanique, Mechanical stress, Tensión mecánica, Mechanische Spannung, Contrainte thermique, Thermal stress, Tensión térmica, Waermespannung, Couche ultramince, Ultrathin films, Diffraction RX, X ray diffraction, Difracción RX, Roentgenbeugung, Essai non destructif, Non destructive test, Ensayo no destructivo, Zerstoerungsfreie Pruefung, Fiabilité, Reliability, Fiabilidad, Zuverlaessigkeit, Gauchissement, Warping, Torcimiento, Mappage, Mapping, Carta de datos, Matrice formage, Die, Matriz formadora, Matrize, Microélectronique, Microelectronics, Microelectrónica, Mikroelektronik, Modèle 3 dimensions, Three dimensional model, Modelo 3 dimensiones, Modèle géométrique, Geometrical model, Modelo geométrico, Méthode mesure, Measurement method, Método medida, Méthode non destructive, Non destructive method, Método no destructivo, Métrologie, Metrology, Metrología, Metrologie, Packaging électronique, Electronic packaging, Packaging electrónico, Phosphure de silicium, Silicon phosphides, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Fertigungsverfahren, Semiconducteur, Semiconductor materials, Semiconductor(material), Halbleiter, Structure 3 dimensions, Three dimensional structure, Estructura 3 dimensiones, Système mesure, Measuring system, Sistema medida, Système sur puce, System on a chip, Sistema sobre pastilla, Système en boîtier, System in package, Embedded QFN package, Non-destructive, Stress, Warpage, and X-ray diffraction

Reliability issues as a consequence of thermal/mechanical stresses created during packaging processes have been the main obstacle towards the realisation of high volume 3D Integrated Circuit (IC) integration technology for future microelectronics. However, there is no compelling laboratory-based metrology that can non-destructively measure or image stress/strain or warpage inside packaged chips, System-on-Chip (SoC) or System-in-Package (SiP), which is identified as a requirement by the International Technology Roadmap for Semiconductors (ITRS). In the work presented here, a triple-axis Jordan Valley Bede D1 X-ray diffractometer is used to develop a novel lab-based technique called X-ray diffraction 3-dimensional surface modelling (XRD/3DSM) for non-destructive analysis of manufacturing process-induced stress/warpage inside completely encapsulated packaged chips. The technique is demonstrated at room temperature and at elevated temperatures up to 115 °C by in situ XRD annealing experiments. The feasibility of this technique is confirmed through the characterisation of die stress inside encapsulated commercially available ultra-thin Quad Flat Non-lead (QFN) packages, as well as die stress in embedded QFN packages at various stages of the chip manufacturing process.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Etat condense: structure, proprietes mecaniques et thermiques, Condensed matter: structure, mechanical and thermal properties, Propriétés mécaniques et acoustiques de l'état condensé, Mechanical and acoustical properties of condensed matter, Propriétés mécaniques des solides, Mechanical properties of solids, Tribologie et dureté, Tribology and hardness, Sciences appliquees, Applied sciences, Metaux. Metallurgie, Metals. Metallurgy, Corrosion, Protection contre la corrosion, Corrosion prevention, Propriétés mécaniques. Rhéologie. Mécanique de la rupture. Tribologie, Mechanical properties and methods of testing. Rheology. Fracture mechanics. Tribology, Dureté, Hardness, Frottement. Usure, Contact of materials. Friction. Wear, Alliage amorphe, Amorphous alloy, Aleación amorfa, Amorphe Legierung, Composition chimique, Chemical composition, Composición química, Chemische Zusammensetzung, Diamant, Diamond, Diamante, Dureté, Hardness, Dureza, Haerte, Essai dureté, Hardness test, Ensayo dureza, Haerteversuch, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Matrice formage, Die, Matriz formadora, Matrize, Microstructure, Microestructura, Mikrogefuege, Microusinage, Micromachining, Micromaquinado, Moulage, Molding, Moldeo, Formverfahren, Mécanique précision, Precision engineering, Mecánica precisión, Feinmechanik, Nanoindentation, Nanoindentacion, Nickel alliage, Nickel alloy, Níquel aleación, Nickellegierung, Propriété mécanique, Mechanical properties, Propiedad mecánica, Résistance oxydation, Oxidation resistance, Resistencia a la oxidación, Stabilité thermique, Thermal stability, Estabilidad térmica, Thermische Stabilitaet, Substitut, Substitute, Substituto, Titane alliage, Titanium alloy, Titanio aleación, Titanlegierung, Tournage, Turning, Torneado, Drehen, Usinabilité, Machinability, Mecanizabilidad, Zerspanbarkeit, Usure, Wear, Desgaste, Verschleiss, Verre, Glass, Vidrio, Glas, Zirconium, Zirconio, 6860B, 8105K, 8105U, 8540H, Glass lens mold, and Micro-cutting

Mold materials for glass lenses with microstructures, such as gratings, require not only excellent mechanical properties, high thermal stability and oxidation resistance, but also sufficient machinability by Single-Point Diamond Turning (SPDT). Our research on Ni-Nb-Zr alloys has shown that one amorphous alloy composition (Ni35Nb40Zr25 at.%) met almost all the requirements for glass lens mold materials. Unfortunately, when fabricating gratings on the mold, the immense wear on the bit, which may be caused by the high hardness of the alloy (more than 10 GPa by the nano-indentation method), made it impossible to cut precise gratings. Consequently, the addition of a fourth element was considered to decrease the hardness. After several experiments, the addition of Ti was found to decrease the hardness. At first, Ti was added to substitute 10% Zr, to give Ni35Nb40Zr15Ti10 at.%. Although this alloy had a lower hardness (9.5 GPa) than Ni35Nb40Zr25 at.%, it still cannot be micro-cut by SPDT. It was then decided to substitute Ti for Ni-Nb instead of Zr. Three samples: Ni30Nb35Zr25Ti10 at.%, Ni28Nb32Zr25Ti15 at.% and Ni25Nb30Zr25-Ti20 at.%, were fabricated for evaluation. Finally, the Ni28Nb32Zr25Ti15 at.% and Ni25Nb30Zr25Ti20 at.% were found to have a low enough hardness to allow for precision machining.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Circuit numérique, Digital circuit, Circuito numérico, Complexité calcul, Computational complexity, Complejidad computación, Echantillonnage, Sampling, Muestreo, Echelle grande, Large scale, Escala grande, Evaluation performance, Performance evaluation, Evaluación prestación, Matrice formage, Die, Matriz formadora, Modélisation, Modeling, Modelización, Méthode Monte Carlo, Monte Carlo method, Método Monte Carlo, Méthode statistique, Statistical method, Método estadístico, Programme SPICE, SPICE, Simulation numérique, Numerical simulation, Simulación numérica, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Technologie MOS, MOS technology, Tecnología MOS, Transistor MOSFET, and MOSFET

With aggressive scaling of CMOS technologies, MOSFET devices are subject to increasing amounts of independent local statistical variability. The causes of these statistical variations and their effects on device performance have been extensively studied, but their impact on circuit performance is still difficult to predict. This paper proposes a method for modeling the impact of random intra-die statistical variations on digital circuit timing. The method allows the variation modeled by large-scale statistical transistor simulations to be propagated up the design flow to the circuit level, by making use of commercial STA and standard cell characterization tools. By using statistical sampling techniques, we achieve close to the accuracy of full SPICE simulation, but with a computational effort similar to that of Statistical Static Timing Analysis, while removing some of the inaccurate assumptions of Statistical Static Timing Analysis.

Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Telecommunications et theorie de l'information, Telecommunications and information theory, Télécommunications, Telecommunications, Radiocommunications, Antennes, Antennas, Alliage Ge Si, Ge-Si alloys, Amplificateur faible bruit, Low noise amplifier, Amplificador bajo ruido, Antenne dipôle, Dipole antenna, Antena dipolo, Antenne intégrée, Integrated antenna, Antena integrada, Chambre anéchoïque, Anechoic room, Circuit MMIC, MMIC, Circuit adaptation, Matching circuit, Circuito adaptación, Conception conjointe, Codesign, Diseño conjunto, Directivité, Directivity, Directividad, Evaluation performance, Performance evaluation, Evaluación prestación, Implémentation, Implementation, Implementación, Matrice formage, Die, Matriz formadora, Optimisation, Optimization, Optimización, Prototype, Prototipo, Transfert énergie, Energy transfer, Transferencia energía, Transistor bipolaire hétérojonction, Heterojunction bipolar transistors, Transmission énergie, Power transmission, Télécommunication sans fil, Wireless telecommunication, Telecomunicación sin hilo, MMIC antenna co-design, SiGe HBT, and low noise amplifier

The implementation of a dipole antenna co-designed and monolithically integrated with a low noise amplifier (LNA) on low resistivity Si substrate (20 Ω · cm) manufactured in 0.35 μm commercial SiGe HBT process with fT/fmax of 170 GHz and 250 GHz is investigated theoretically and experimentally. An air gap is introduced between the chip and a reflective ground plane, leading to substantial improvements in efficiency and gain. Moreover, conjugate matching conditions between the antenna and the LNA are exploited, enhancing power transfer between without any additional matching circuit. A prototype is fabricated and tested to validate the performance. The measured 10-dB gain of the standalone LNA is centered at 58 GHz with a die size of 0.7 mm × 0.6 mm including all pads. The simulated results showed antenna directivity of 5.1 dBi with efficiency higher than 70%. After optimization, the co-designed LNA-Antenna chip with a die size of 3 mm × 2.8 mm was characterized in anechoic chamber environment. A maximum gain of higher than 12 dB was obtained.

General chemistry, physical chemistry, Chimie générale, chimie physique, Energy, Énergie, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Electroénergétique, Electrical power engineering, Conversion directe et accumulation d'énergie, Direct energy conversion and energy accumulation, Conversion photoélectrique, Photoelectric conversion, Energie, Energy, Energie naturelle, Natural energy, Energie solaire, Solar energy, Conversion photovoltaïque, Photovoltaic conversion, Cellules solaires. Cellules photoélectrochimiques, Solar cells. Photoelectrochemical cells, Application industrielle, Industrial application, Aplicación industrial, Cellule solaire organique, Organic solar cells, Cellule solaire, Solar cell, Célula solar, Couche active, Active layer, Capa activa, Etude comparative, Comparative study, Estudio comparativo, Evaluation performance, Performance evaluation, Evaluación prestación, Homogénéité, Homogeneity, Homogeneidad, Matrice formage, Die, Matriz formadora, Matériau revêtu, Coated material, Material revestido, Revêtement protecteur, Protective coatings, Revestimiento protector, Structure flexible, Flexible structure, Estructura flexible, Conversion ascendante, Upconversion, Film homogeneity, Flexible substrates, Ink formulation, Organic photovoltaics, Slot-die coating, and Solvent

The transfer from lab scale to industrial application is one of the challenges for organic photovoltaics. For this, non halogenated formulations are a decisive need for the upscaling process, as are roll-to-toll (R2R) compatible methods. Devices processed with o-xylene using slot-die coating as a sheet-to-sheet technique show a reduced efficiency on a larger scale compared to lab scale solar cells. By using a mixture of high and low volatile solvents which selectively dissolve one component, the film homogeneity and the efficiency is dramatically improved. The slot-die coated active layers for solar cells processed from non-halogenated solvents show device efficiencies above 3% on flexible substrates.

General chemistry, physical chemistry, Chimie générale, chimie physique, Energy, Énergie, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Matériaux, Materials, Energie, Energy, Energie naturelle, Natural energy, Energie solaire, Solar energy, Conversion photovoltaïque, Photovoltaic conversion, Cellules solaires. Cellules photoélectrochimiques, Solar cells. Photoelectrochemical cells, Acide butyrique, Butyric acid, Butírico ácido, Addition étain, Tin addition, Adición estaño, Aluminium, Aluminio, Argent, Silver, Plata, Aérosol, Aerosols, Aerosol, Cellule solaire organique, Organic solar cells, Chlore composé organique, Organic chlorine compounds, Chrome, Chromium, Cromo, Collection courant, Current collection, Colección corriente, Composé du fullerène, Fullerene compounds, Condition météorologique, Atmospheric condition, Condición meteorológica, Couche ITO, ITO layers, Empilement, Stacking, Apilamiento, En continu, Continuous process, En continuo, Ester, Ethylène téréphtalate polymère, Ethylene terephthalate polymer, Etileno tereftalato polímero, Etude comparative, Comparative study, Estudio comparativo, Etude expérimentale, Experimental study, Estudio experimental, Evaluation performance, Performance evaluation, Evaluación prestación, Film polymère, Polymer films, Matrice formage, Die, Matriz formadora, Matériau revêtu, Coated material, Material revestido, Mélange polymère, Polymer blends, Ombre, Shadow, Sombra, Oxyde d'indium, Indium oxide, Indio óxido, Processus fabrication, Production process, Proceso fabricación, Procédé discontinu, Batch process, Procedimiento discontínuo, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Pulvérisation irradiation, Sputtering, Pulverización irradiación, Revêtement protecteur, Protective coatings, Revestimiento protector, Styrènesulfonate polymère, Styrenesulfonate polymer, Estireno sulfonato polímero, Thiophène dérivé polymère, Thiophene derivative polymer, Tiofeno derivado polímero, Couche de transport de trous, Hole transport layer, ITO, Procédé roll-to-roll, Roll-to-roll process, Aerosol printing, Ag grid, ITO-free, Non-chlorinated solvents, and R2R coating

This work reports on indium tin oxide (ITO)-free organic solar cells with roll to roll (R2R) processed organic functional layers. The device stack comprises a chromium―aluminum―chromium (Cr―Al―Cr) electron contact layer on a polyethylene terephthalate (PET) film, a photoactive layer of poly(3-hexylthiophene) (P3HT): (6,6)-phenyl C61 butyric acid methyl ester (PCBM), a hole transport layer of Poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate) (PEDOT:PSS) and a silver (Ag) grid for current collection. For the photoactive layer the non-halogenated solvent o-Xylene was used in order to reduce the impact on health and environment for R2R coating on ambient atmospheric conditions. The Cr―Al―Cr layers were sputtered onto the PET rolls in a batch process while the photoactive layer as well as the hole transport layer were applied in a continuous R2R process by slot die coating. The Ag grid was either thermally evaporated through a shadow mask as reference process or deposited by aerosol printing as a more production compatible process. Device efficiencies up to 2.9% on an active area of 1.1 cm2 were obtained with no difference for the method of grid processing. These experimental results demonstrate that R2R coated organic functional layers in ITO-free devices obtain the same device performance as compared to spin coated laboratory cells.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Essais, mesure, bruit et fiabilité, Testing, measurement, noise and reliability, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Analyse dommage, Failure analysis, Análisis avería, Assemblage brasage tendre, Soldered joint, Junta soldada, Assemblage circuit intégré, Integrated circuit bonding, Cavité dans réseau, Void, Cavidad en red, Choc thermique, Thermal shock, Choque térmico, Circuit intégré, Integrated circuit, Circuito integrado, Composé intermétallique, Intermetallic compound, Compuesto intermetálico, Connexion par billes, Flip chip bonding, Conexión espesada, Cuivre, Copper, Cobre, Défaillance, Failures, Fallo, Equation vitesse, Rate equation, Ecuación velocidad, Essai choc, Impact test, Ensayo choque, Fiabilité, Reliability, Fiabilidad, Fissuration, Cracking, Agrietamiento, Fissure, Crack, Fisura, Interconnexion, Interconnection, Interconexión, Matrice formage, Die, Matriz formadora, Matériau fragile, Brittle material, Material frágil, Propagation fissure, Crack propagation, Propagación fisura, Puce à bosses, Flip-chip, Vitesse propagation, Propagation velocity, and Velocidad propagación

The intermetallic compound (IMC) evolution and the thermal-mechanical reliability of Sn―3.0Ag―0.5Cu (SAC305) solder joints were studied using air-to-air thermal shock testing of 100-μm-pitch peripheral-row flip chip assemblies. Flip chips assembled on organic substrates were subjected to air-to-air thermal shock testing between ―55 °C and 125 °C, and the samples were removed at regular intervals for cross-sectioning and failure analysis. It was seen that on the die side, after 2000 cycles, all of the (Cu,Ni)3Sn4 had transferred to (Cu,Ni)6Sn5 due to strong cross-pad interaction between the chip-side Ni pad and substrate-side Cu pad, and thus, there was no premature solder cracking possibly due to the absence of dual IMC structure. On the substrate-side Cu interface, the Cu3Sn growth was hindered, and thus there was very little increase in Kirkendall voids in the Cu3Sn after 2000 cycles. Therefore, there was no premature brittle failure in the intermetallic. Failure analysis shows that the cracks in the outermost corner solder joint started to form after 2000 cycles near the chip-side pad, and the cracks propagated in the solder matrix around the IMC like a ring to create solder open. From the experimental data, crack propagation rate equation parameters and characteristic mean life were determined.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Instruments, appareillage, composants et techniques communs à plusieurs branches de la physique et de l'astronomie, Instruments, apparatus, components and techniques common to several branches of physics and astronomy, Techniques et équipements généraux, General equipment and techniques, Capteurs (chimiques, optiques, électriques, de mouvement, de gaz, etc.); télédétection, Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Capteur mesure, Measurement sensor, Captador medida, Caractéristique électrique, Electrical characteristic, Característica eléctrica, Couche ultramince, Ultrathin films, Matrice formage, Die, Matriz formadora, Mesure contrainte, Stress measurement, Microrégisseur, Microcontroller, Microcontrolador, Monitorage, Monitoring, Monitoreo, Packaging électronique, Electronic packaging, Packaging electrónico, Propriété mécanique, Mechanical properties, Propiedad mecánica, Silicium, Silicon, Silicio, Structure flexible, Flexible structure, Estructura flexible, Surface arrière, Back surface, Superficie atrás, Système autonome, Autonomous system, Sistema autónomo, Vêtement, Clothing, Vestidura, and 0707D

Ultra-thin chips of less than 20 μm become flexible, allowing integration of silicon IC technology with highly flexible electronics such as food packaging sensor systems or healthcare and sport monitoring tags as wearable patches or even directly in clothing textile. The ultra-thin chips in these products will be bent to a very high curvature, which puts a large strain on the chips during use. In this paper a modified four-point bending method is presented, which is capable of measuring chip stress at high curvatures. The strength of several types of ultra-thin chips is evaluated, including stand-alone ultra-thin test chips and back-thinned 20 μm thick microcontrollers, as well as assemblies containing integrated ultra-thin microcontroller chips. The effect of chip thickness, bending direction and backside finish on strength and minimum bending radius is investigated using the modified four point bending method. The effect of bonding ultra-thin chips to flexible foils on the assembly strength and minimum bending radius is evaluated as well as the effect of bending on electrical properties of the bonded microcontroller dies. .

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Essais, mesure, bruit et fiabilité, Testing, measurement, noise and reliability, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Analyse dommage, Failure analysis, Análisis avería, Caractéristique électrique, Electrical characteristic, Característica eléctrica, Défaillance, Failures, Fallo, Matrice formage, Die, Matriz formadora, Optimisation, Optimization, Optimización, Seuil tension, Voltage threshold, Umbral tensión, Technologie tranchée, Trench technology, Tecnología trinchera, Transistor MOSFET, and MOSFET

In this paper, the failure modes of a 60 V power UMOSFET firstly have been discussed by analyzing the test data of the die, and our hypothesis is that the merger of the P-base regions under the trench leads to larger on-resistance and threshold voltage of 60 V UMOSFET. To further verify the hypothesis, the formula for the resistance of the drift region has been derived, and the simulating model of UMOSFET has been given with various mergers of the P-base regions. Then the simulation model has been corrected and the parameters of UMOSFET have been optimized. The re-design of 60 V UMOSFET has been taped out successfully, with its electric parameters totally meeting the requirements.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Mémoire accès direct, Random access memory, Memoria acceso directo, Mémoire non volatile, Non volatile memory, Memoria no volátil, Charge thermique, Thermal load, Carga térmica, Circuit intégré, Integrated circuit, Circuito integrado, Compatibilité électromagnétique, Electromagnetic compatibility, Compatibilidad electromagnética, Déformation, Deformation, Deformación, Empilement, Stacking, Apilamiento, Encapsulation plastique, Plastic packaging, Encapsulación plástica, Gauchissement, Warping, Torcimiento, Interconnexion, Interconnection, Interconexión, Matrice formage, Die, Matriz formadora, Mémoire accès direct dynamique, Dynamic random access memory, Méthode élément fini, Finite element method, Método elemento finito, Packaging électronique, Electronic packaging, Packaging electrónico, Pastille électronique, Wafer, Pastilla electrónica, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Silicium, Silicon, Silicio, Technologie PMOS, PMOS technology, Tecnología PMOS, Température ambiante, Room temperature, Temperatura ambiente, Transistor MOS, MOS transistor, Trou interconnexion, Via hole, and Agujero interconexión

This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moiré are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different.

Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Intelligence artificielle, Artificial intelligence, Reconnaissance des formes. Traitement numérique des images. Géométrie algorithmique, Pattern recognition. Digital image processing. Computational geometry, Algorithme, Algorithm, Algoritmo, Evaluation performance, Performance evaluation, Evaluación prestación, Matrice formage, Die, Matriz formadora, Méthode statistique, Statistical method, Método estadístico, Pastille électronique, Wafer, Pastilla electrónica, Précision élevée, High precision, Precisión elevada, Segmentation, Segmentación, Vision ordinateur, Computer vision, and Visión ordenador

This study presents a computer vision-based wafer dies counting algorithm. It utilises the single model and multi-model RANSAC (Random Sample Consensus) algorithms to detect the circular contour of a wafer and its dicing lanes, respectively. Statistical analysis is performed to extract the characteristics of layout so that missed dicing lanes can be supplemented. The number of integral dies is counted after segmenting individual dies based on the complete layout information. The experimental results show that the proposed algorithm has high counting accuracy and good computational efficiency.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Domaines interdisciplinaires: science des materiaux; rheologie, Cross-disciplinary physics: materials science; rheology, Science des matériaux, Materials science, Nanomatériaux et nanostructures : fabrication et caractèrisation, Nanoscale materials and structures: fabrication and characterization, Divers, Other topics in nanoscale materials and structures, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Electronique de puissance, alimentations électriques, Power electronics, power supplies, Argent, Silver, Plata, Assemblage brasage tendre, Soldered joint, Junta soldada, Assemblage circuit intégré, Integrated circuit bonding, Basse température, Low temperature, Baja temperatura, Caractéristique électrique, Electrical characteristic, Característica eléctrica, Carbure de silicium, Silicon carbide, Silicio carburo, Commutation, Switching, Conmutación, Conductivité thermique, Thermal conductivity, Conductividad térmica, Dispositif puissance, Power device, Dispositivo potencia, Durabilité, Durability, Durabilidad, Durée vie fatigue, Fatigue life, Longevidad fatiga, Electronique puissance, Power electronics, Electrónica potencia, Fatigue thermique, Thermal fatigue, Fatiga térmica, Fiabilité, Reliability, Fiabilidad, Frittage, Sintering, Sinterización, Haute température, High temperature, Alta temperatura, Matrice formage, Die, Matriz formadora, Microassemblage, Microassembling, Micromontaje, Nanomatériau, Nanostructured materials, Nanoparticule, Nanoparticle, Nanopartícula, Packaging électronique, Electronic packaging, Packaging electrónico, Propriété mécanique, Mechanical properties, Propiedad mecánica, and SiC

The last several years have seen the advent of silicon carbide (SiC) power devices operating at temperatures well above 125 °C. These devices have the potential to provide higher switching speed and lower on-state losses with higher thermal conductivity. Developing reliable technologies for packaging is now the main hurdle to successful operation of SiC based power electronics at high temperature. This paper evaluates a novel silver nano-particle colloid material that has been suggested for use as a die attachment for high temperature environments. The material synthesis together with fundamental mechanical and electrical properties is presented relative to the low temperature sintering process. Using thermal fatigue data measured for this material, a low cycle fatigue curve for the silver nano-particle colloid was developed. A Coffin―Manson relationship was derived for the solder; which together with calculated strains in the joint, allows the low cycle fatigue life of the die attachment to be predicted.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Domaines interdisciplinaires: science des materiaux; rheologie, Cross-disciplinary physics: materials science; rheology, Science des matériaux, Materials science, Matériaux particuliers, Specific materials, Matériaux poreux; matériaux granulaires, Porous materials; granular materials, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Oscillateurs, résonateurs, synthétiseurs, Oscillators, resonators, synthetizers, Algorithme, Algorithm, Algoritmo, Empilement, Stacking, Apilamiento, Horloge, Clock, Reloj, Matrice formage, Die, Matriz formadora, Matériau granulaire, Granular material, Material granular, Optimisation, Optimization, Optimización, Packaging électronique, Electronic packaging, Packaging electrónico, Synthétiseur fréquence, Frequency synthesizer, Sintetizador frecuencia, Temps retard, Delay time, Tiempo retardo, 8105R, 3D ICs, 3D clock tree synthesis, Clock skew, Design methodology, and On-package variation

A 3D stacked IC is made of multiple dies possibly with heterogeneous process technologies. Therefore, the die-to-die variation between the stacked dies creates on-package variation in a 3D chip. In this paper, we analyze the effect of on-package variation on the 3D clock trees and address the problem of on-package variation aware layer embedding in 3D clock tree synthesis. The layer embedding problem is divided into two sub-problems: clock node embedding and clock edge embedding. While the clock node embedded problem has been intensively investigated by the previous 3D clock tree synthesis flows because the solution directly determines the TSV allocation, the clock edge embedding problem has not been fully addressed yet. We show in this work that a careful clock edge embedding can greatly reduce the impact of on-package variation on the 3D clock skew, thereby enhancing chip yield, and propose a two-step solution to the problem of on-package variation aware layer embedding of clock edges. Specifically, we formulate the edge embedding problem into a problem of maximizing the sharing of layers among the clock paths to minimize the impact of on-package variation globally and solve it efficiently, followed by applying a fine-grained refinement technique to balance the clock latency locally among the clock paths. From the experiments with Benchmark circuits, we confirm that compared to the results produced by the conventional on-package variation unaware layer embedding of clock edges, the proposed algorithm is able to improve the chip yield by 6.2-25.8% and 5.3-44.4% for 2-layered and 4-layered 3D designs, respectively.