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Wire bonding (Electronic packaging), Time value of money, Production engineering, Semiconductor industry, Electronic packaging, Mathematical models, and Integrated circuit bonding

The semiconductor industry in Taiwan has received excellent performance ratings in the past. SinoPac’s statistics in January, 2016 found that two of the top four global packaging and testing companies are from Taiwan, including ASE Group and SPIL. In the IC packaging process, the wire bonding machine requires careful attention. It is also costly at approximately 50% of the equipment investment. Thus, this paper focuses on wire bonding machines’ production problems. According to the on-site interviews, three key control modules are identified, which may change a machine to an out-of-control state and are responsible for 90% of the defective products. A mathematical model is developed to determine the optimal production time of an imperfect production process. Taking the time value of money, the objective is to minimise the total of the set-up cost, inventory cost and the defect cost. Besides applying MacLaurin Series, a math property and an effective solution range are derived to help obtain near-optimal solutions. For the justification of solution quality, the bisection method working on practical data is used. Finally, managerial insights are explored from observed outputs through the changes of various parameters. Moreover, these explorations are confirmed by experts in this field. [ABSTRACT FROM PUBLISHER]

ELECTRIC contacts, INTEGRATED circuit bonding, PRINTED circuits, SEMICONDUCTOR wafer bonding, and MICROPOSITIONING systems

We propose a new simple and low-cost alignment method utilizing electric contact for die stacking on an interposer or a printed circuit board. Without any expensive aligning/bonding equipment assisted by microscopy, we successfully stacked and bonded two silicon dies on a printed circuit board achieving alignment accuracy of $20~\mu \text{m}$ by utilizing only cheap equipment: manual micropositioners, a stage, a stand, a heat gun, a hot plate, and a power supply. In the proposed method, conductive alignment marks are fabricated on the bonding surfaces, and the electric contact between them are used to characterize misalignment. Therefore, the proposed method does not require any expensive complex microscopy equipment for alignment. In addition, alignment can be quickly and simply examined in situ by detecting electrical conduction during bonding. In experiment, alignment accuracy better than $20~\mu \text{m}$ and 100% bonding yield was measured in testing of 1800 bonds connecting two silicon interposer dies which were stacked on a printed circuit board by the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents the combination of an innovative assembly and packaging process utilising solid liquid inter diffusion (SLID) Cu-Sn interconnects within bespoke ceramic substrates that have been produced using additive manufacturing (AM). The resultant process chain supports the integration and packaging of power electronics for harsh environment applications. Here, the authors explore how the bond strength and composition of Cu-Sn SLID interconnects vary during exposure to thermal-mechanical load profiles. Samples of Cu-Sn are exposed to thermal loading up to 300°C and integrated mechanical loading via high random frequency vibrations (1 and 2000 Hz). In parallel, micro-extrusion printing methods in which high-viscosity ceramic pastes are dispensed through cylindrical fine nozzles (2–250 µm) using CNC-controlled motion has enabled complex 3D geometries to be fabricated. Additional secondary conductor deposition after firing the ceramic substrate enables the electronic circuitry to be generated without dedicated tooling, masks, or templates. This work presents the first fully 3D-printed ceramic-based electronic substrates. To demonstrate the applications of this printing method, a 555 timer circuit with flashing LED has been printed and the components surface mount assembled. The resultant ceramic substrates are dense, mechanically robust, and the reflowed circuit functions exactly as intended. [ABSTRACT FROM AUTHOR]

SEMICONDUCTOR wafer bonding, HYDROPHILIC surfaces, SURFACE chemistry, HYDROPHILIC interactions, INTEGRATED circuit bonding, and BONDING of semiconductors

Highlights • Bonding and de-bonding of thin Si layer was processed at low temperature (<250 °C). • Unlike conventional wafer bonding such as smart-cut based SOI or similar substrate, wafer flip-up/down is not needed. • Hydrophilic surface was formed via plasma treatment instead of high temperature bonding annealing. Abstract We studied low temperature (<250 °C) transfer of 8 in. full sized thin Si wafer layer on the SiO 2 /Si substrate without any wafer flip up/down and subsequent high temperature process. This method includes temporary bonding of carrier wafer with bonding material at 200 °C, grinding or etching substrate, and transfer layer at 250 °C. Thickness values of transferred thin Si layer using bulk Si and silicon-on-insulator (SOI) wafer substrates are 87 μm and 216 nm on the SiO 2 /Si substrate, respectively. Plasma treatment under N 2 and O 2 mixture ambient assisting to form hydrophilic surface was carried out during bonding process and enhanced bonding strength was confirmed by contact angle measurement. Our wafer bonding process can be feasible to form various monolithic 3D devices due to thin Si layer transfer and low temperature process. [ABSTRACT FROM AUTHOR]

INTEGRATED circuit bonding, SOLID-liquid interfaces, DIFFUSION bonding (Metals), HERMETIC sealing, MICROELECTROMECHANICAL systems, and GOLD compounds

In this paper, wafer-level AuSn/Pt solid–liquid interdiffusion bonding for hermetic encapsulation of microelectromechanical systems (MEMS) is evaluated. Although AuSn is used for bonding of ICs, the implementation of AuSn diffusion bonding in MEMS applications requires thorough understanding of its compatibility with the complete layer stack including adhesion, buffer, and metallization layers. Partitioning of the layer stacks is possible in MEMS devices consisting of several silicon wafers since the device wafer carrying functional structures and the encapsulation wafer have different restrictions on process integration and applicable metal deposition techniques. In this paper, CMOS/MEMS compatible sputtered platinum is utilized on the device wafer as a contact metallization for Au–Sn metallized cap wafer. The role of the platinum layer thickness as well as the nickel and molybdenum buffer layers on mechanical reliability were tested. The mechanical shear and tensile tests were performed for samples after bonding as well as after high-temperature storage and thermal shock tests. The results were rationalized based on the combined microstructural, thermodynamic, and fracture surface analyses. High-strength and thermodynamically stable bonds were achieved, exhibiting shear strength up to ~180 MPa and tensile strength up to ~80 MPa. Platinum was consumed completely during bonding and was observed to dissolve mainly into the (Au,Pt)Sn phase. Thicker platinum layer (200 versus 100 nm) increased the (Au,Pt)Sn phase thickness and resulted in higher strength. The molybdenum buffer layer under the platinum metallization increased the tensile strength significantly. [ABSTRACT FROM AUTHOR]

extrusion, printing, integrated circuit bonding, three-dimensional printing, integrated circuit packaging, microfabrication, assembling, copper alloys, power semiconductor devices, high random frequency vibrations, microextrusion printing methods, power electronics, bond strength, solid liquid inter diffusion, packaging, micro-extrusion printing methods, Cu-Sn, Engineering (General). Civil engineering (General), and TA1-2040

This paper presents the combination of an innovative assembly and packaging process utilising solid liquid inter diffusion (SLID) Cu-Sn interconnects within bespoke ceramic substrates that have been produced using additive manufacturing (AM). The resultant process chain supports the integration and packaging of power electronics for harsh environment applications. Here, the authors explore how the bond strength and composition of Cu-Sn SLID interconnects vary during exposure to thermal-mechanical load profiles. Samples of Cu-Sn are exposed to thermal loading up to 300°C and integrated mechanical loading via high random frequency vibrations (1 and 2000 Hz). In parallel, micro-extrusion printing methods in which high-viscosity ceramic pastes are dispensed through cylindrical fine nozzles (2–250 µm) using CNC-controlled motion has enabled complex 3D geometries to be fabricated. Additional secondary conductor deposition after firing the ceramic substrate enables the electronic circuitry to be generated without dedicated tooling, masks, or templates. This work presents the first fully 3D-printed ceramic-based electronic substrates. To demonstrate the applications of this printing method, a 555 timer circuit with flashing LED has been printed and the components surface mount assembled. The resultant ceramic substrates are dense, mechanically robust, and the reflowed circuit functions exactly as intended.

SEMICONDUCTOR wafer bonding, SPUTTERING (Physics), INTEGRATED circuit bonding, BONDING of semiconductors, and ARGON

We study covalent bonds between p-doped Si wafers (resistivity ∼10 Ω cm) fabricated on a recently developed 200 mm high-vacuum system. Oxide- and void free interfaces were obtained by argon (Ar) or neon (Ne) sputtering prior to wafer bonding at room temperature. The influence of the sputter induced amorphous Si layer at the bonding interface on the electrical behavior is accessed with temperature-dependent current-voltage measurements. In as-bonded structures, charge transport is impeded by a potential barrier of 0.7 V at the interface with thermionic emission being the dominant charge transport mechanism. Current-voltage characteristics are found to be asymmetric which can tentatively be attributed to electric dipole formation at the interface as a result of the time delay between the surface preparation of the two bonding partners. Electron beam induced current measurements confirm the corresponding asymmetric double Schottky barrier like band-alignment. Moreover, we demonstrate that defect annihilation at a low temperature of 400 °C increases the electrical conductivity by up to three orders of magnitude despite the lack of recrystallization of the amorphous layer. This effect is found to be more pronounced for Ne sputtered surfaces which is attributed to the lighter atomic mass compared to Ar, inducing weaker lattice distortions during the sputtering. [ABSTRACT FROM AUTHOR]

COPPER wire, METAL bonding, LASER heating, SHEAR strength, INTEGRATED circuit interconnections, INTEGRATED circuit bonding, and ULTRASONICS

As the need for integrated circuits increase year after year, researchers around the globe are constantly experimenting for innovative approaches to use copper wire as a medium of interconnectivity. Copper is being used as an alternative to replace gold to produce interconnections in microelectronics. However, the use of copper wire is known to pose threats to low-k devices with thin structure. The impact of hard copper free air ball onto bonding surfaces is undesirable as it can damage the bond pad and the silicon die. In-situ heating of free air ball is expected to reduce its hardness and mitigate columnar grains. This research paper investigates the effects of in-situ free air ball laser heating on bonding strength and grain structure for 99.999% purity (5N) copper wire bonding. Wire bonding was performed on bond pads consisting of NiPdAu metallization and was wire bonded under 16 different temperature conditions. Results of this study showed significantly higher as-bonded ball shear strengths and reduced columnar grains when in-situ laser heating is applied. The results of this study can be helpful for semiconductor plastic packaging with copper wire bonding on thin die structures by further improving copper wire bonding quality without the need to use excessive bonding temperature, higher bonding force and excessive ultrasonic energy. [ABSTRACT FROM AUTHOR]

SEMICONDUCTOR wafer bonding, INTEGRATED circuit bonding, POLYIMIDE films, SOLID lubricants, and MATERIALS science

A simplified low-temperature wafer-level hybrid bonding process using Cu pillar bumps and photosensitive adhesive was reported, wherein Cu/SnAg/Ni-P micro interconnects were formed to achieve electrical interconnect and the sealing around adhesive played the role of mechanical reinforcement. The proposed hybrid bonding method has been applied to 8 inch wafer to wafer bonding. Two kinds of photosensitive adhesives, i.e., polyimide and dry film, were selected for adhesive bonding. Excess adhesive on the Cu/SnAg micro bumps was properly removed using simple and low cost lithograph process. In order to prevent the adhesive trapping in the metal bonding interface, the height of the Cu/SnAg micro bumps was 2 μm higher than that of the adhesives. Although hybrid bonding using polyimide and dry film can achieve seam free bonding interface, shear test results indicate that bonding strength using dry film is more robust, and dry film is more suitable for hybrid bonding in three-dimensional integration applications. [ABSTRACT FROM AUTHOR]

ANALOG-to-digital converters, INTEGRATED circuit design, INTEGRATED circuit bonding, SIGNAL-to-noise ratio, and NEURAL circuitry

In Jung et al. (Electron Lett 48(10):557-558, 1), a double noise coupling scheme was proposed for ΔΣ analog-to-digital converters (ADCs) to achieve wideband and high accuracy performance combined with low power consumption. In this paper, an improved version of double noise coupling ΔΣ ADC is presented. The improved architecture reduces the power consumption significantly, by reducing the output swing of the second integrator in the modulator. Also, the improved double noise coupling ΔΣ ADC relaxes the feedback timing of the modulator using a triple sampling technique (Kanazawa et al. in IEEE Custom Integrated Circuit Conference, 2). Thus, there is no need to have high-speed comparator and DEM circuitry even for high-speed applications. By using both techniques, the performance of the double noise coupling ΔΣ ADC can be improved significantly. [ABSTRACT FROM AUTHOR]

ACTIVE pixel sensors, INTEGRATED circuit bonding, SYNCHROTRON radiation sources, SYNCHROTRON radiation, INTEGRATED circuits, and SEMICONDUCTOR nuclear counters

The VIPIC1 readout integrated circuit was designed for X-ray Photon Correlation Spectroscopy experiments that are typically performed using mono-energetic (8 keV) X-rays at a synchrotron radiation facility. The device is a pixel detector with sparsification and parallel readout from the groups, yielding high timing resolution. Recent improvements in bonding alignment of wafers resulted in deliveries of 3D bonded wafers. The stacks, bonded with both the Cu-Cu thermo-compression method and the Cu DBI bonding method, yielded operational devices that have been tested. Chips (with a pixel pitch of 80~\mu\m) were also bonded to silicon pixelated sensors (with a pixel pitch of 100~\mu\m) and the assemblies were exposed to X-ray sources for the first time. The paper focuses on the test results, including the calibrated noise (ENC) and the conversion gain. The noise measured corresponded to 39~\e^ - and 70~\e^ - , respectively for the readout channels that were not connected and connected to the sensor diodes. The conversion gain varied from 43 to 52~\mu\V/e^ - as a function of the bias current in the front-end block. Essentially all the pixels on a small prototype were operational. [ABSTRACT FROM PUBLISHER]

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Domaines interdisciplinaires: science des materiaux; rheologie, Cross-disciplinary physics: materials science; rheology, Science des matériaux, Materials science, Méthodes de dépôt de films et de revêtements; croissance de films et épitaxie, Methods of deposition of films and coatings; film growth and epitaxy, Electrodépôt, Electrodeposition, electroplating, Méthodes de nanofabrication, Methods of nanofabrication, Autoassemblage, Self-assembly, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Agent intelligent, Intelligent agent, Agente inteligente, Assemblage circuit intégré, Integrated circuit bonding, Autoassemblage, Self-assembly, Biomimétique, Biomimetics, Boucle fermée, Closed loop, Bucle cerrado, Commande automatique, Automatic control, Control automático, Couche sacrificielle, Sacrificial layer, Capa sacrificial, Couche épaisse, Thick films, Cuivre, Copper, Dépôt électrolytique, Electrodeposition, Eau, Water, Empilement compact, Close packing, Apilamiento compacto, Epoxyde résine, Epoxy resin, Epóxido resina, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Fluidique, Fluidics, Lithographie, Lithography, Microfluidique, Microfluidics, Modèle 3 dimensions, Three dimensional model, Modelo 3 dimensiones, Montage surface composant, Surface mount technology, Mécanique précision, Precision engineering, Mecánica precisión, Pastille électronique, Wafers, Photorésist, Photoresists, Polymère photosensible, Light sensitive polymer, Polímero fotosensible, Procédé fabrication, Manufacturing processes, Production par lot, Batch production, Réseau carré, Square lattices, Structure petite échelle, Small scale structure, Estructura pequeña escala, Système temps réel, Real time systems, Traceur radioactif, Radioactive tracers, 4785N, 8116D, 8116N, 8540H, Electroplating, Microfabrication, and SU-8

Self-assembly (SA) is a bio-inspired key coordination mechanism for swarms of intelligent agents as well as a pervasive bottom-up methodology for the fabrication of heterogeneous micro- and nanosystems. Analytical studies of SA at small scales are therefore highly relevant for many technological applications. In this paper we present an innovative design and fabrication process for three-dimensional polymeric microtiles conceived as passive vehicles to investigate the dynamics of fluidic SA at sub-millimeter scale. The microtiles are fabricated out of the superposition of two structural SU-8 layers featuring chiral copies of the same centro-symmetric pattern. They can coordinate laterally in water independently of their vertical orientation to form close-packed square lattice clusters. The microtiles embed a central marker enabling the real-time optical tracking and automated closed-loop control of their fluidic SA. The fabrication process makes use of a thick sacrificial copper layer and allows the wafer-level batch production of tens of thousands of microtiles, in line with the massively parallel nature of SA.

Electronics, Electronique, Condensed state physics, Physique de l'état condensé, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Domaines interdisciplinaires: science des materiaux; rheologie, Cross-disciplinary physics: materials science; rheology, Science des matériaux, Materials science, Méthodes de dépôt de films et de revêtements; croissance de films et épitaxie, Methods of deposition of films and coatings; film growth and epitaxy, Techniques de revêtement par pulvérisation, Spray coating techniques, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Dispositifs optoélectroniques, Optoelectronic devices, Energie, Energy, Energie naturelle, Natural energy, Energie solaire, Solar energy, Conversion photovoltaïque, Photovoltaic conversion, Cellules solaires. Cellules photoélectrochimiques, Solar cells. Photoelectrochemical cells, Metaux. Metallurgie, Metals. Metallurgy, Transformation de matériaux métalliques, Production techniques, Traitements de surface, Surface treatment, Absorbeur, Absorber, Absorbente, Absorption 2 photons, Two photon absorption, Absorción 2 fotones, Assemblage circuit intégré, Integrated circuit bonding, Cellule solaire, Solar cell, Célula solar, Chalcopyrite, Calcopirita, Chalkopyrit, Couche mince, Thin film, Capa fina, Duennschicht, Couche tampon, Buffer layer, Capa tampón, Diffraction RX, X ray diffraction, Difracción RX, Roentgenbeugung, Dépôt projection, Spray coating, Depósito proyección, Spritzbeschichten, Effet température, Temperature effect, Efecto temperatura, Temperatureinfluss, Gain, Ganancia, Indium, Indio, Matériau absorbant, Absorbent material, Material absorbente, Matériau cristallin, Crystalline material, Material cristalino, Recuit mise en solution, Solution heat treatment, Recocido disolución, Loesungsgluehen, Relation ordre, Ordering, Relación orden, Site cristallographique, Crystallographic site, Sitio cristalográfico, Solution aqueuse, Aqueous solution, Solución acuosa, Waesserige Loesung, Spectre Raman, Raman spectrum, Espectro Raman, Spectrométrie Raman, Raman spectrometry, Espectrometría Raman, Spectrométrie dispersive, Dispersive spectrometry, Espectrometría dispersiva, Stoechiométrie, Stoichiometry, Estequiométría, Stoechiometrie, Sulfure d'indium, Indium sulfide, Indio sulfuro, Indiumsulfid, Technologie CSP, Chip scale packaging, Température substrat, Substrat temperature, Temperatura substrato, Température superficielle, Surface temperature, Temperatura superficial, Oberflaechentemperatur, Thiourée, Thiourea, Tiourea, 7830N, 8460J, Cellule solaire à bande intermédiaire, Intermediate band solar cell, In2S3, Pyrolyse par projection, Spray pyrolysis, Chemical spray pyrolysis, EDX, Raman spectroscopy, and XRD

Indium sulfide (In2S3) thin films are of interest as buffer layers in chalcopyrite absorber based solar cells; and as media providing two-photon absorption for intermediate-band solar cells. We investigated the suitability of chemical spray pyrolysis (CSP) for growing In2S3 thin films in a structural order where indium atoms are preferentially in the octahedral sites. We sprayed aqueous or alcoholic solutions of indium chloride (InCl3) and thiourea (SC(NH2)2) precursors onto a substrate with surface temperatures (Ts) of 205, 230, 275 and 320 °C. The as-deposited films grown from aqueous solutions were annealed in 5% H2S containing atmosphere at 500 °C. We used Raman spectroscopy, X-ray diffraction and Energy Dispersive X-ray spectroscopy to evaluate the effect of growth temperature and the effect of annealing on the film structure and stoichiometry. The use of alcoholic solvent instead of aqueous allows us to use much lower Ts while preserving the quality of the β-In2S3 films obtained. Similarly, films with increased stoichiometry and quality are present at a higher Ts; and when annealed. The annealing of the films grown at Ts of 205 °C results in a much higher gain of the crystal quality compared to the gain when annealing the films grown at Ts of 320 °C, although the quality remain higher when deposited at Ts of 320 °C. Simultaneously with the increase of the film quality, there is a sign of increased quality of the crystal ordering with indium in the octahedral sites. Such a crystal ordering favor the use of CSP deposited In2S3 films in the intermediate band solar cells.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Action humidité, Humidity effect, Acción humedad, Adhérence, Adhesion, Adherencia, Assemblage circuit intégré, Integrated circuit bonding, Caractéristique électrique, Electrical characteristic, Característica eléctrica, Contrainte thermique, Thermal stress, Tensión térmica, Contrainte électrique, Electric stress, Tensión eléctrica, Courant électrique, Electric current, Corriente eléctrica, Cycle thermique, Thermal cycle, Ciclo térmico, Déformation élastique, Elastic deformation, Deformación elástica, Effet contrainte, Stress effects, Effet température, Temperature effect, Efecto temperatura, Essai cisaillement, Shear test, Ensayo cortante, Rupture, Ruptura, Technologie puce sur verre, Chip on glass packaging, Tecnología COG, Vieillissement thermique, Thermal ageing, Envejecimiento térmico, Viscoélasticité, Viscoelasticity, and Viscoelasticidad

This paper reports the adhesion and electrical properties of chip-on-glass (COG) assembly undergoing the coupling loads of temperature, electric current and stress (hygrothermal stress or thermal stress). Firstly, the effects of loading rate and coupling loads on the adhesive force of COG assembly were studied by shear test. The maximum shear force of COG assembly firstly increases and then decreases with increasing loading rate in range of 10-70 μm/s, peaks at the loading rate of 50 μm/s. When the COG assembly was exposed in the coupling loads of temperature, electric current and hygrothermal stress, its maximum shear force decreases with the increase of hygrothermal aging time. However, as for thermal cycling aging time increases, the maximum shear force increases initially and then decreases for the COG assembly under the coupling loads of temperature, electric current and thermal stress. The functions of the maximum shear force with aging time were obtained by fitting experiment data. Secondly, the real-time resistances of COG assembly during shear test and aging process were detected using two-point probe. In shear process, the real-time resistance increases insignificantly in elastic deformation stage but increases rapidly in viscoelastic deformation stage prior to the fracture. Due to the combined influences of temperature, electric current and stress, the resistance increases remarkably with the increase of hygrothermal aging time and it increases slightly with the increase of thermal cycling aging time. However, the real-time resistance exhibits circulation changes corresponding to thermal cycling. Finally, the relationship of resistance with the maximum shear force of energized COG assembly versus environmental aging times was studied.