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Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Diminution coût, Cost lowering, Reducción costes, Estimateur, Estimator, Estimador, Estimation paramètre, Parameter estimation, Estimación parámetro, Matrice formage, Die, Matriz formadora, Méthode Monte Carlo, Monte Carlo method, Método Monte Carlo, Méthode statistique, Statistical method, Método estadístico, Simulation numérique, Numerical simulation, Simulación numérica, Système intelligent, Intelligent system, Sistema inteligente, Temps retard, Delay time, Tiempo retardo, Transistor, Logical effort, Monte Carlo, Statistical timing analysis, and Timing yield estimation

Considerable effort has been expended in the EDA community during the past decade in trying to cope with the so-called statistical timing problem. In this paper, we not only present a fast and approximate gate delay model called stochastic logical effort (SLE) to capture the effect of statistical parameter variations on the delay but also combine this model with a previously proposed transistor level smart Monte Carlo method to construct ISLE timing yield estimator. The results demonstrate that our approximate SLE model can capture the delay variations and ISLE achieves the same accuracy as the standard Monte Carlo estimator with a cost reduction of about 180 x on the average for ISCAS'85 benchmark circuits and in the existence of both inter- and intra-die variations.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits analogiques, Analog circuits, Matériel informatique, Hardware, Equipements d'entrée-sortie, Input-output equipment, Circuit analogique, Analog circuit, Circuito analógico, Circuit intégré, Integrated circuit, Circuito integrado, Circuit à signal mixte, Mixed signal circuit, Circuito de señal mixto, Espacement, Spacing, Espaciamiento, Gain, Ganancia, Routeur, Router, Signal analogique, Analog signal, Señal analógica, Solution optimale, Optimal solution, Solución óptima, Système conversationnel, Interactive system, Sistema interactivo, Système sur puce, System on a chip, Sistema sobre pastilla, Analog routing, Global routing, Interactive routing, SIAR, and Splitting graph

As analog and mixed-signal (AMS) circuitry gains increasing portions in modern SoCs, automatic analog routing is becoming more and more important. However, routing for analog circuits has always been an extremely challenging task due to complicated electrical and geometrical constraints. Due to these constraints, current analog routers often fail to obtain a routing solution that the designer wants. To incorporate the designer's expertise during routing, a customized real-time interactive analog router is attracting increasing concerns in industry. This paper presents a fast customized real-time interactive analog router called SIAR. A key feature of SIAR is that it allows for real-time interactions between the router and the designer. The designer can try different guiding points by moving the cursor in the user window and SIAR will return and display the corresponding routing solution in real-time, such that the designer could choose the most satisfactory one. The guiding points are very important for the designer to obtain satisfactory routing solutions, even for routing solutions with analog matching constraints by setting symmetric guiding points. A new splitting graph based routing model is presented to efficiently search the routing path and record the number of turns/vias during searching by efficient tile splitting operations. SIAR supports different routing modes such as point-to-point, point-to-module and module-to-module. An efficient connecting point selection method is presented such that an optimal routing solution is preserved when connecting to a module. Different design rules such as variable wire and via width/spacing rules, along with the same-net spacing rules, are supported in SIAR. Moreover, a global routing stage is presented to speedup the routing process for large designs. Experimental results are promising.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Basse tension, Low voltage, Baja tensión, Circuit logique, Logic circuit, Circuito lógico, Ecart type, Standard deviation, Desviación típica, Economies d'énergie, Energy savings, Ahorros energía, Evaluation performance, Performance evaluation, Evaluación prestación, Impureté, Impurity, Impureza, Logique seuil, Threshold logic, Lógica umbral, Modélisation, Modeling, Modelización, Nanotechnologie, Nanotechnology, Nanotecnología, Porte logique, Logic gate, Puerta lógica, Processus stochastique, Stochastic process, Proceso estocástico, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Seuil tension, Voltage threshold, Umbral tensión, Temps retard, Delay time, Tiempo retardo, Transistor MOS complémentaire, Complementary MOS transistor, Transistor MOS complementario, Valeur moyenne, Mean value, Valor medio, Core speed variation, Footer transistor, Many-core, Multi-Vdd design, Multi-Vt design, Multi-core, Process variation, Process voltage and temperature variations, Random dopant fluctuation, Simulation, System level modeling, and Voltage scaling

Process variation creates core-speed discrepancy among the core in a many-core platforms. Random variation is one of the important components that contributes into core-speed discrepancy. In this paper, we propose a novel technique that uses footer transistors to reduce the impact of random process variation on delay and power in a many-core platform. Process variation is due to many fundamental deficiencies, impurities, and imperfections during the fabrication process at the nano-scale technologies. The results of this variation have a direct impact on two key parameters of the CMOS transistor: threshold voltage and gate length, which have major implication on the core speed and power. The random component of this variation is mostly attributed to the random-dopant fluctuation, which results in threshold voltage discrepancy among the cores. The proposed technique reduces the random dopant fluctuation by lowering the dopant density and then compensating the threshold voltage using a footer transistor. The results show a reduction of the total standard deviation from 25% down to 17% using the proposed method. Furthermore, the average energy saving of 30 different applications mapped on a many-core platform is improved by around 5%, and the performance by around 6%. .

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Convertisseurs de signal, Signal convertors, Algorithme, Algorithm, Algoritmo, Architecture réseau, Network architecture, Arquitectura red, Circuit intégré, Integrated circuit, Circuito integrado, Consommation électricité, Electric power consumption, Consumo electricidad, Economies d'énergie, Energy savings, Ahorros energía, Electronique faible puissance, Low-power electronics, Empilement, Stacking, Apilamiento, Energie minimale, Minimum energy, Energía mínima, Etat actuel, State of the art, Estado actual, Gestion tâche, Task scheduling, Gestión labor, Globalement asynchrone localement synchrone, Globally asynchronous locally synchronous, Globalmente asincrono localmente sincrono, Implémentation, Implementation, Implementación, Mappage, Mapping, Carta de datos, Modèle 3 dimensions, Three dimensional model, Modelo 3 dimensiones, Méthode partition, Partition method, Método partición, Optimisation, Optimization, Optimización, Partitionnement, Partitioning, Subdivisión, Processeur multicoeur, Multicore processor, Procesador MultiNúcleo, Réseau interconnexion, Interconnection network, Red interconexión, Structure 3 dimensions, Three dimensional structure, Estructura 3 dimensiones, Système sur puce, System on a chip, Sistema sobre pastilla, 3-Dimensional SoCs, Power balancing, System energy, Thermal constraint, and Voltage-frequency island

Three dimensional (3-D) multi-core SoC has been recognized as a promising solution for implementing complex applications with lower system energy. Recently, voltage-frequency island (VFI)-based design paradigm was widely adopted for energy optimization. However, the existing work commonly targeted 2-D platform, which cannot handle the exacerbated thermal issues and the increased solution space from 3-D integration. In this paper, we propose an optimization framework targeting VFI-based 3-D multi-core SoCs to minimize system energy meanwhile still meeting task deadline and thermal constraints. Our framework conducts at an earlier design phase in which designers have the freedom to determine the core stacks and map them into the hardware platform. Besides energy-aware task scheduling, we also conduct core stacking and task adjusting to balance the powers across the chip for thermal optimization. Moreover, by treating each core stack as a unity, the complicated problem of core mapping and VFI partitioning in 3-D platform can be simplified as a 2-D one. Experimental results demonstrate that on average our framework can achieve an energy reduction of 15.8% over the prior thermal balancing algorithm [17] (X. Zhou, J. Yang, Y. Xu, et al. Thermal-aware task scheduling for 3D multicore processors, IEEE Trans. Parallel Distrib. Syst. (TPDS), 21(1) (2010), 60-71.). Moreover, on average a reduction of 4.8 °C in peak temperature is achieved by our framework, compared with the state-of-the-art energy optimization scheme [8] (U.Y. Ogras, R. Marculescu, P. Choudhary, et al. Voltage-frequency island partitioning for GALS-based networks-on-chip, in: ACM/IEEE Design Automation Conference (DAC), 2007, pp. 110-115.).

Chemistry, Chimie, Energy, Énergie, Chemical industry parachemical industry, Industrie chimique et parachimique, Nanotechnologies, nanostructures, nanoobjects, Nanotechnologies, nanostructures, nanoobjets, Physics, Physique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Etat condense: structure electronique, proprietes electriques, magnetiques et optiques, Condensed matter: electronic structure, electrical, magnetic, and optical properties, Propriétés optiques, spectroscopie et autres interactions de la matière condensée avec les particules et le rayonnement, Optical properties and condensed-matter spectroscopy and other interactions of matter with particles and radiation, Photoluminescence, Domaines interdisciplinaires: science des materiaux; rheologie, Cross-disciplinary physics: materials science; rheology, Science des matériaux, Materials science, Nanomatériaux et nanostructures : fabrication et caractèrisation, Nanoscale materials and structures: fabrication and characterization, Matériaux nanocristallins, Nanocrystalline materials, Points quantiques, Quantum dots, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Electronique moléculaire, nanoélectronique, Molecular electronics, nanoelectronics, Acétylacétone, Acetylacetone, Enzyme, Enzymes, Graphène, Graphene, Hyperfréquence, Microwave radiation, Nanomatériau, Nanostructured materials, Peroxyde d'hydrogène, Hydrogen peroxide, Peróxido de hydrogeno, Photoluminescence, Point quantique, Quantum dots, 8105T, 8105U, 8107B, 8107T, and 8535B

We report a microwave sequential bottom-up route to produce green and blue luminescent graphene quantum dots (g-GQDs and b-GQDs) with size-tunable and switchable functionalities by tailoring the diameter size and functional groups via microwave carbonization and aromatization processes from acetylacetone as a starting organic solvent. The b-GQDs as the final product show only one emission peak at 433 nm and pH-independent blue luminescence, because two-step microwave irradiation could reduce the size and the oxygen-functional groups of the g-GQDs as an intermediate product. Also, the b-GQDs provide an exemplar enzyme-free platform for hydrogen peroxide detection through the electrochemical sensing due to much higher electron density and electron donating properties. In contrast, the g-GQDs show two different switchable photoluminescent emissions at ~460 nm (PI) and ~500 nm (P2): the P1 emission with sky-blue fluorescence originates from randomly conjugated oxygen-functional groups on the basal plane and/or edge of the g-GQDs and the P2 emission with green fluorescence results from quasi-molecular fluorophores formed by the electronic coupling of carboxylic acid groups.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Circuit arithmétique, Arithmetic circuit, Circuito aritmético, Algorithme, Algorithm, Algoritmo, Circuit intégré, Integrated circuit, Circuito integrado, Circuit multiplicateur, Multiplying circuits, Contraste image, Image contrast, Imagen contraste, Diminution coût, Cost lowering, Reducción costes, Echelle gris, Gray scale, Escala gris, Haute fréquence, High frequency, Alta frecuencia, Implémentation, Implementation, Implementación, Logiciel, Software, Logicial, Masquage, Masking, Enmascaramiento, Qualité image, Image quality, Calidad imagen, Réseau porte programmable, Field programmable gate array, Red puerta programable, Traitement image, Image processing, Procesamiento imagen, Contrast enhancement, Logarithmic image processing, and Multiplierless log-hybrid low-complexity hardware architecture

A novel colour image enhancement architecture combining a Tonal Correction algorithm and a high frequency emphasis circular symmetric filter is implemented in hardware forming a colour image contrast enhancement system of low complexity. The architecture utilizes efficient log-domain calculations, resulting in multiplier-less operations and eliminates costly hardware division. Furthermore, the modularity of the fundamental design enables its ease of incorporation into larger and more complex designs with little modification. The design can be used for both grayscale and RGB colour images by processing each channel individually and the system can serve as a post enhancement module for improved colour rendition. The unit can be configured for the enhancement of over-exposed (too bright) and under-exposed (too dark) images based on adjustable parameters. The architecture easily fits on a basic Spartan III FPGA for low-cost realization evaluation and a Virtex 5 ML505 for real-time use. Results of the implementation and simulation are provided and compared with the software version and show that the system produces images with improved colour contrast and rendition compared to well known image enhancement algorithms such as RGB colour Homomorphic filtering. It also performs better than the Homomorphic filter and the MSRCR for faded colour images. .

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Matériel informatique, Hardware, Systèmes informatiques, Computer systems, Apprentissage renforcé, Reinforcement learning, Aprendizaje reforzado, Caractéristique énergétique, Energy characteristic, Característica energética, Circuit intégré, Integrated circuit, Circuito integrado, Condition non stationnaire, Non stationary condition, Condición no estacionaria, Consommation électricité, Electric power consumption, Consumo electricidad, Economies d'énergie, Energy savings, Ahorros energía, Etude comparative, Comparative study, Estudio comparativo, Evaluation performance, Performance evaluation, Evaluación prestación, Logiciel, Software, Logicial, Méthode adaptative, Adaptive method, Método adaptativo, Optimisation, Optimization, Optimización, Ordonnancement, Scheduling, Reglamento, Processeur, Processor, Procesador, Processus Markov, Markov process, Proceso Markov, Processus semi markovien, Semimarkovian process, Proceso semi markoviano, Réseau électrique, Electrical network, Red eléctrica, Système informatique, Computer system, Sistema informático, Système référence, Reference system, Sistema referencia, Traitement en ligne, On line processing, Tratamiento en línea, Variation temporelle, Time variation, Variación temporal, Power management, Semi-Markov decision process, and Temporal difference learning

This paper presents a hierarchical dynamic power management (DPM) framework based on reinforcement learning (RL) technique, which aims at power savings in a computer system with multiple I/O devices running a number of heterogeneous applications. The proposed framework interacts with the CPU scheduler to perform effective application-level scheduling, thereby enabling further power savings. Moreover, it considers non-stationary workloads and differentiates between the service request generation rates of various software application. The online adaptive DPM technique consists of two layers: component-level local power manager and system-level global power manager. The component-level PM policy is pre-specified and fixed whereas the system-level PM employs temporal difference learning on semi-Markov decision process as the model-free RL technique, and it is specifically optimized for a heterogeneous application pool. Experiments show that the proposed approach considerably enhances power savings while maintaining good performance levels. In comparison with other reference systems, the proposed RL-based DPM approach, further enhances power savings, performs well under various workloads, can simultaneously consider power and performance, and achieves wide and deep power-performance tradeoff curves. Experiments conducted with multiple service providers confirm that up to 63% maximum energy saving per service provider can be achieved.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Etude théorique. Analyse et conception des circuits, Theoretical study. Circuits analysis and design, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits analogiques, Analog circuits, Circuit analogique, Analog circuit, Circuito analógico, Circuit intégré analogique, Analogue integrated circuits, Complexité calcul, Computational complexity, Complejidad computación, Conception assistée, Computer aided design, Concepción asistida, Conception circuit, Circuit design, Diseño circuito, Dimensionnement, Dimensioning, Dimensionamiento, Etat actuel, State of the art, Estado actual, Fiabilité, Reliability, Fiabilidad, Implantation circuit intégré, Integrated circuit layout, Implémentation, Implementation, Implementación, Méthode noyau, Kernel method, Método núcleo, Optimisation sous contrainte, Constrained optimization, Optimización con restricción, Programmation multiobjectif, Multiobjective programming, Programación multiobjetivo, Programme SPICE, SPICE, Propriété géométrique, Geometrical properties, Propiedad geométrica, Simulation circuit, Circuit simulation, Analog integrated circuits, Automatic module generator, Electronic design automation, Floorplan-aware circuit sizing, and Multi-objective optimization

This paper presents a methodology for analog IC circuit-level sizing and optimization, which takes into account the layout geometrical properties, by introducing a simple and general description that permits the inclusion of the floorplan generation in the sizing optimization loop with negligible computational costs. The usage of a modified NSGA-II state-of-the-art multi-objective multi-constraint optimization kernel enables the efficient exploration of design tradeoffs, while the inclusion of corner cases and the usage of the industrial circuit simulators (HSPICE® Eldo® or Spectre®) ensures the accuracy and reliability of the solutions. Several layout templates that enclose the constraints defined by the designer are used to generate multiple floorplan solutions for each sizing solution during the synthesis process, giving the optimizer pertinent and accurate geometric layout information, e.g., area, width, length, wasted area, etc. Additionally, a built-in technology independent module generator facilitates the instantiation of multiple versions of each device, further increasing the exploration of possible geometric combinations and consequently packing of the floorplan with a minimum of wasted area. The developed tool, AIDA-C, implements the proposed approach, and is validated for both classical and new analog circuit structures using the UMC 130 nm design process.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Circuit arithmétique, Arithmetic circuit, Circuito aritmético, Circuit VLSI, VLSI circuit, Circuito VLSI, Circuit additionneur, Summing circuits, Circuit intégré, Integrated circuit, Circuito integrado, Circuit logique, Logic circuit, Circuito lógico, Conception circuit intégré, Integrated circuit design, Consommation électricité, Electric power consumption, Consumo electricidad, Diminution coût, Cost lowering, Reducción costes, Electronique faible puissance, Low-power electronics, Energie minimale, Minimum energy, Energía mínima, Etat actuel, State of the art, Estado actual, Horloge, Clock, Reloj, Logique retenue, Carry logic, Processeur 64 bits, 64 bit Processor, Procesador 64 bits, Rendement énergétique, Energetic efficiency, Rendimiento energético, Structure arborescente, Tree structure, Estructura arborescente, Temps retard, Delay time, Tiempo retardo, Adders, Hybrid adders, Low-energy, and VLSI design

An energy efficient adder design based on a hybrid carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and backwards from the MSB. The incidence at a midpoint significantly accelerates the addition. This acceleration together with combining low-cost ripple-carry and carry-chain circuits, yields energy efficiency compared to other adder architectures. The optimal midpoint is analytically formulated and its closed-form expression is derived. To avoid the quadratic RC delay growth in a long carry chain, it is optimally repeated. The adder is enhanced in a tree-like structure for further acceleration. 32, 64 and 128-bit adders targeting 500 MHz and 1 GHz clock frequencies were designed in 65 nm technology. They consumed 11-18% less energy compared to adders generated by state-of-the-art EDA synthesis tool.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuit séquentiel, Sequential circuit, Circuito secuencial, Effet non linéaire, Non linear effect, Efecto no lineal, Etude expérimentale, Experimental study, Estudio experimental, Horloge, Clock, Reloj, Programmation linéaire, Linear programming, Programación lineal, Temps minimal, Minimum time, Tiempo mínimo, Optimisation circuit, Circuit optimization, Optimización circuito, Clock skew scheduling, Ellipsoid method, and Multi-parameter

Clock skew scheduling is a powerful technique for circuit optimization. Conventionally it can be formulated as a minimum cost-to-time ratio cycle (MCR) problem, which can be solved efficiently by a set of specialized network optimization algorithms. However, those algorithms can only handle one single parameter at a time, for example, the clock period, the timing slack or the yield. This inflexibility limits the applicability of the scheduling technique because in a real design one may need to consider multiple parameters simultaneously. In this paper, we introduce a multi-parameter extension to the MCR problem. Furthermore, a convex nonlinear extension is also considered. In particular, we generalize Lawler's algorithm, which is based on the bisection strategy. When there is more than one parameter, the bisection strategy is naturally replaced by the ellipsoid method. More importantly, the ellipsoid method does not require the knowledge of all constraints explicitly in prior. Instead, for each iteration, only a constraint that is violated by the current solution is required. This constraint turns out to be a negative cycle in our formulation, which can be detected efficiently. As a result, our proposed method could gain up to 12 x run-time speedup for linear problems compared with a general linear programming solver and more than 700 x run-time speedup for nonlinear problems compared with a general convex programming solver based on our experimental results.

Geology, Géologie, Mechanics acoustics, Mécanique et acoustique, Metallurgy, welding, Métallurgie, soudage, Condensed state physics, Physique de l'état condensé, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Metaux. Metallurgie, Metals. Metallurgy, Assemblage et découpage thermique: aspects métallurgiques, Joining, thermal cutting: metallurgical aspects, Brasage, Brazing. Soldering, Aimantation, Magnetization, Imanación, Magnetisieren, Argent alliage, Silver alloy, Plata aleación, Silberlegierung, Brasage avec refusion, Reflow soldering, Soldeo con refusión, Aufschmelzloeten, Calorimétrie différentielle balayage, Differential scanning calorimetry, Análisis calorimétrico barrido exploración, Differentialrasterkalorimetrie, Cobalt alliage, Cobalt alloy, Cobalto aleación, Cobaltlegierung, Cuivre alliage, Copper alloy, Cobre aleación, Kupferlegierung, Effet champ magnétique, Magnetic field effect, Efecto campo magnético, Magnetischer Feldeffekt, Etain alliage, Tin alloy, Estaño aleación, Zinnlegierung, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Fer alliage, Iron alloy, Hierro aleación, Eisenlegierung, Fiabilité, Reliability, Fiabilidad, Zuverlaessigkeit, Matériau composite, Composite material, Material compuesto, Verbundwerkstoff, Métal transition alliage, Transition metal alloy, Metal transición aleación, Uebergangsmetallegierung, Nanomatériau magnétique, Magnetic nanomaterial, Nanomaterial magnético, Nanoparticule, Nanoparticle, Nanopartícula, Packaging électronique, Electronic packaging, Packaging electrónico, Particule magnétique, Magnetic particles, Perte magnétique, Iron loss, Pérdida magnética, Magnetischer Verlust, Propriété thermomécanique, Thermomechanical properties, Propriedad termomecánica, Brasure sans plomb, and Lead free solder

Sn-Ag-Cu (SAC) alloys are regarded as the most promising alternative for traditional Pb-Sn solders used in electronic packaging applications. However, the higher reflow temperature requirement, possible intermetallic formation, and reliability issues of SAC alloys generate several key challenges for successful adoption of Pb-free solder for next generation electronic packaging needs. Localized heating in interconnects can alleviate thermal stresses by preventing subjection of entire package to the higher reflow temperatures associated with the SAC solders. It had been demonstrated that SAC solder-FeCo magnetic nanoparticles (MNPs) composite paste can be reflowed locally with AC magnetic fields, enabling interconnect formation in area array packages while minimizing eddy current heating in the printed circuit board. Solder/magnetic nanocomposite pastes with varying MNP concentration were reflowed using AC magnetic fields. Differential scanning calorimetry results show a reduced undercooling of the composite pastes with the addition of MNPs. TEM results show that the FeCo MNPs are distributed in Sn matrix of the reflowed solder composites. Optical and SEM micrographs show a decrease in Sn dendrite regions as well as smaller and more homogeneous dispersed Ag3Sn with the addition of MNPs. The MNPs promote Sn solidification by providing more heterogeneous nucleation sites at relatively low undercoolings. The mechanical properties were measured by nanoindentation. The modulus, hardness, and creep resistance, increase with the MNP concentration. The enhanced mechanical properties are attributed to grain boundary and dispersion strengthening. The reflow of solder composites have been modeled based on eddy current power loss in the substrate and magnetic power losses in the solder bumps. Induction reflow of pure solder bumps (<300 μm) in an area array package using 500 Oe magnetic field at 300 kHz requires excessive eddy current power loss in the substrate, resulting in extreme temperatures that lead to blistering and delamination of the substrate. Solder-MNP composites with modest MNP loading showed temperature increases sufficient to achieve solder reflow when subjected to the same AC magnetic fields. Thermomechanical behavior of a solder joint was also modeled under cyclic temperature variations. The stress and strain are highly localized at the interface between solder and substrate. Plastic work accumulated per cycle can be used for lifetime prediction. In this article we review lead-containing and lead-free solder systems, and the electronic packaging technologies pertinent to soldering process. Recent research on the effects of MNPs on localized heating, microstructure evolution, mechanical properties, and thermomechanical reliability are summarized.

Cognition, Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Informatique théorique, Theoretical computing, Algorithmique. Calculabilité. Arithmétique ordinateur, Algorithmics. Computability. Computer arithmetics, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Sciences biologiques et medicales, Biological and medical sciences, Sciences biologiques fondamentales et appliquees. Psychologie, Fundamental and applied biological sciences. Psychology, Biophysique moleculaire, Molecular biophysics, Structure en biologie moléculaire, Structure in molecular biology, Structure tridimensionnelle, Tridimensional structure, Accélérateur, Accelerator, Acelerador, Algorithme flou, Fuzzy algorithm, Algoritmo borroso, Bioinformatique, Bioinformatics, Bioinformática, Biopolymère, Biopolymer, Biopolímero, Classification, Clasificación, Code longueur variable, Variable length code, Código longitud variable, Complexité algorithme, Algorithm complexity, Complejidad algoritmo, Conception circuit, Circuit design, Diseño circuito, Intervalle confiance, Confidence interval, Intervalo confianza, Logique floue, Fuzzy logic, Lógica difusa, Mesure complexité, Complexity measure, Medida complexidad, Mesure distance, Distance measurement, Plus proche voisin, Nearest neighbour, Vecino más cercano, Protéine, Protein, Proteína, Réseau neuronal, Neural network, Red neuronal, Réseau porte programmable, Field programmable gate array, Red puerta programable, Structure tertiaire, Tertiary structure, Estructura terciaria, Traitement incertitude, Uncertainty handling, Field programmable gate arrays, Fuzzy k-nearest-neighbor algorithm, K-NN classification algorithm, Lempel-Ziv algorithm, Protein secondary structure prediction, and Protein structural class

Correct prediction of protein secondary structural classes is vital for the prediction of tertiary structures and understanding of their function. Most of the prediction algorithms require lengthy computation time. Nearest neighbor ― complexity distance measure (NN-CDM) algorithm was one of the significant prediction algorithms using Lempel―Ziv (LZ) complexity-based distance measure, but it is slow and ineffective in handling uncertainties. To solve the problems, we propose fuzzy NN-CDM (FKNN-CDM) algorithm that incorporates the confidence level of prediction results and enhance the prediction process by designing hardware architecture that implements the proposed algorithm in an FPGA board. Highest average prediction accuracies for Z277 and 25PDB datasets using proposed algorithm are 84.12% and 47.81% respectively, with 15 times faster computation using an Altera DE2-115 FPGA board.

Cognition, Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Physique statistique, thermodynamique, et systèmes dynamiques non linéaires, Statistical physics, thermodynamics, and nonlinear dynamical systems, Dynamique non linéaire et systèmes dynamiques non linéaires, Nonlinear dynamics and nonlinear dynamical systems, Synchronisation ; oscillateurs couplés, Synchronization ; coupled oscillators, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Intelligence artificielle, Artificial intelligence, Connexionnisme. Réseaux neuronaux, Connectionism. Neural networks, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Dispositifs micro- et nanoélectromécaniques (mems/nems), Micro- and nanoelectromechanical devices (mems/nems), Circuit mémoire, Memory circuit, Circuito memoria, Mémoire non volatile, Non volatile memory, Memoria no volátil, Méthode Newton, Newton method, Método Newton, Retard, Delay, Retraso, Réseau neuronal, Neural network, Red neuronal, Synchronisation, Synchronization, Sincronización, Synthèse commande, Control synthesis, Síntesis control, Système paramètre variable, Time varying system, Sistema parámetro variable, Système à retard, Delay system, Sistema con retardo, Temps retard, Delay time, Tiempo retardo, Memristor, Filippov solution, and Memristor-based neural networks

In this paper, synchronization of memristor-based neural networks (MNNs) with time-varying delays is investigated. By employing the Newton-Leibniz formulation and inequality technique, the controller with state or output coupling is designed to obtain global exponential synchronization of MNNs. The obtained delay-dependent conditions can be checked easily and they also enrich and improve the results in earlier publications. Finally, one numerical example is given to demonstrate the effectiveness of the obtained results.

Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Informatique théorique, Theoretical computing, Algorithmique. Calculabilité. Arithmétique ordinateur, Algorithmics. Computability. Computer arithmetics, Intelligence artificielle, Artificial intelligence, Reconnaissance et synthèse de la parole et du son. Linguistique, Speech and sound recognition and synthesis. Linguistics, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Algorithme génétique, Genetic algorithm, Algoritmo genético, Algorithme recherche, Search algorithm, Algoritmo búsqueda, Algorithme évolutionniste, Evolutionary algorithm, Algoritmo evoluciónista, Analyse circuit, Network analysis, Análisis circuito, Analyse signal, Signal analysis, Análisis de señal, Analyse symbolique, Symbolic analysis, Análisis simbolico, Circuit analogique, Analog circuit, Circuito analógico, Estimation erreur, Error estimation, Estimación error, Etude expérimentale, Experimental study, Estudio experimental, Fonction transfert, Transfer function, Función traspaso, Intelligence artificielle, Artificial intelligence, Inteligencia artificial, Intelligence en essaim, Swarm intelligence, Inteligencia de enjambre, Méthode heuristique, Heuristic method, Método heurístico, Méthodologie, Methodology, Metodología, Optimisation, Optimization, Optimización, Programmation multiobjectif, Multiobjective programming, Programación multiobjetivo, Recherche locale, Local search, Busca local, Recuit simulé, Simulated annealing, Recocido simulado, Signal analogique, Analog signal, Señal analógica, Signal faible, Small signal, Señal débil, Taux erreur, Error rate, Indice error, Technologie MOS, MOS technology, Tecnología MOS, Texte, Text, Texto, Traitement signal, Signal processing, Procesamiento señal, Transistor effet champ, Field effect transistor, Transistor efecto campo, Analyse texte, Text analysis, Análisis de textos, Programme SPICE, SPICE, Programa SPICE, Transistor MOSFET, MOSFET, Analog circuits, Modified nodal analysis, Multi-objective optimization, and Simplified symbolic analysis

In this paper, an evolutionary-based multi-objective criterion is introduced for simplified symbolic small-signal analysis of analog circuits containing MOSFETs. After circuit analysis via modified nodal analysis technique, the derived exact symbolic transfer function of the circuit behavior is automatically simplified. In contrast to traditional simplification criteria, the main objective of our criterion is to control the final simplification error rate. The proposed simplification methodology can be performed by such optimization algorithms as local-search algorithms, heuristic algorithms, swarm intelligence algorithms, etc. In this paper, a hybrid algorithm based on genetic algorithm and simulated annealing is applied to validate the proposed methodology. It is remarkable that all steps including netlist text processing, symbolic analysis, post-processing, simplification, and numerical analysis are consecutively derived in an m-file MATLAB program. The proposed methodology was successfully tested on three analog circuits, and the numerical results were compared with HSPICE.

Cognition, Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Instruments, appareillage, composants et techniques communs à plusieurs branches de la physique et de l'astronomie, Instruments, apparatus, components and techniques common to several branches of physics and astronomy, Techniques et équipements généraux, General equipment and techniques, Capteurs (chimiques, optiques, électriques, de mouvement, de gaz, etc.); télédétection, Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Telecommunications et theorie de l'information, Telecommunications and information theory, Théorie de l'information, du signal et des communications, Information, signal and communications theory, Théorie du signal et des communications, Signal and communications theory, Signal, bruit, Signal, noise, Détection, estimation, filtrage, égalisation, prédiction, Detection, estimation, filtering, equalization, prediction, Analyse composante indépendante, Independent component analysis, Analisis componente independiente, Aveugle, Blind, Ciego, Calcul formel, Computer algebra, Cálculo formal, Effet non linéaire, Non linear effect, Efecto no lineal, Etalonnage, Calibration, Contraste, Etude expérimentale, Experimental study, Estudio experimental, Identification aveugle, Blind identification, Identificación ciega, Information mutuelle, Mutual information, Información mutual, Mesure, Measurement, Medida, Mélange signal, Signal mixing, Mezcla señal, Méthode séparation, Separation method, Método separación, Source linéaire, Linear source, Fuente lineal, Séparation aveugle, Blind separation, Separación ciega, Séparation source, Source separation, Separación señal, Transformation échelle, Scale transformation, Transformación escala, Transistor effet champ sensible ion, Ionosensible field effect transistor, Transistor efecto campo sensible ión, Transistor effet champ, Field effect transistor, Transistor efecto campo, Capteur intelligent, Intelligent sensors, Sensor inteligente, Ion-selective field-effect transistors, Nonlinear blind source separation, Post-nonlinear mixtures, and Smart sensors

The response of ion-sensitive field-effect transistors (ISFETs) can be seriously affected in mixed-ion solutions by different interfering ions. As has been demonstrated, this problem can be addressed using nonlinear semi-blind source separation (BSS) algorithms based on post-non-linear mixtures in which nonlinear transforms must be computed using supervised samples, i.e. calibration points for known concentrations of the main ion. In order to eliminate the cost of collecting such samples, this paper introduces a novel non-linear BSS algorithm that employs linearizing transforms computed only with unsupervised information. The scale indeterminacy of this transform is removed using a prior on the sources based on magnitude bounding and, besides, gaussianization is generalized by using a kernel estimator. Experiments with real ISFET measurements demonstrate that this BSS algorithm achieves a level of accuracy similar to that of the semi-blind counterpart based on independent component analysis and outperforms a post-nonlinear BSS algorithm which minimizes the mutual information.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Autres dispositifs multijonctions. Transistors de puissance. Thyristors, Other multijunction devices. Power transistors. Thyristors, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Algorithme, Algorithm, Algoritmo, Capacité électrique, Capacitance, Capacitancia, Caractéristique électrique, Electrical characteristic, Característica eléctrica, Circuit intégré CMOS, CMOS integrated circuits, Circuit intégré, Integrated circuit, Circuito integrado, Circuit logique, Logic circuit, Circuito lógico, Circuit numérique, Digital circuit, Circuito numérico, Conception circuit, Circuit design, Diseño circuito, Conception optimale, Optimal design, Concepción optimal, Consommation électricité, Electric power consumption, Consumo electricidad, Critère conception, Design criterion, Criterio concepción, Electronique puissance, Power electronics, Electrónica potencia, Evaluation performance, Performance evaluation, Evaluación prestación, Extensibilité, Scalability, Estensibilidad, Extraction paramètre, Parameter extraction, Extracción parámetro, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Fiabilité, Reliability, Fiabilidad, Interconnexion, Interconnection, Interconexión, Lithographie, Lithography, Litografía, Logique seuil, Threshold logic, Lógica umbral, Porte logique, Logic gate, Puerta lógica, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Seuil tension, Voltage threshold, Umbral tensión, Simulation numérique, Numerical simulation, Simulación numérica, Temps retard, Delay time, Tiempo retardo, Transistor puissance, Power transistor, Transistor potencia, Asynchronous router, Die-to-die variation, Environment variation, ISCAS85, Variation-aware methodology, and Within-die variation

In submicron technology, during the fabrication process factors like lithography and lens defect can change some of the physical parameters of transistors and interconnects. This change can modify the transistor electrical characteristics such as current, threshold voltage and gate capacitance, and thus it causes variation in power, delay and performance of the circuit. Process variation has become one of designer's challenges to the point that in below 45 nm technology it is considered as the most important issue in reliability. Power consumption and transistors variation are limiting factors to physical scalability. In this paper, we propose two approaches to reduce D2D and WID variations effects on digital CMOS circuits, at design time. The first approach concerns a variation-aware algorithm capable of extracting optimal design parameters to decrease variation and power. The second approach, using transistor stacking will help further reduce variation and power. Applying the algorithm on a digital design and according to parameters behavior in the presence of variation, we extract for each parameter value that will lead to power and variation reduction. On the other hand, with the stacking approach only basic gates are considered and subsequently gate configurations that reduce power and variation are proposed. The proposed approaches could be used identically for synchronous and asynchronous circuits. To prove this claim, we apply our approaches to a network-on-chip asynchronous router and a circuit from the ISCAS85 benchmark. All simulations are done in 32 nm technology using the HSPICE tool. The proposed algorithm similar to Monte Carlo simulation achieves the same results; however with lower execution time. The application of stacking approach to both asynchronous router and ISCAS85 circuit reduces variation effects up to 40.9% and 13.35%, respectively.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuit intégré, Integrated circuit, Circuito integrado, Algorithme, Algorithm, Algoritmo, Capacité électrique, Capacitance, Capacitancia, Circuit VLSI, VLSI circuit, Circuito VLSI, Commutation, Switching, Conmutación, Dimensionnement, Dimensioning, Dimensionamiento, Dissipation énergie, Energy dissipation, Disipación energía, Espacement, Spacing, Espaciamiento, Interconnexion, Interconnection, Interconexión, Microprocesseur, Microprocessor, Microprocesador, Multicouche, Multiple layer, Capa múltiple, Méthode partition, Partition method, Método partición, Optimisation sous contrainte, Constrained optimization, Optimización con restricción, Partitionnement, Partitioning, Subdivisión, Système n dimensions, Multidimensional system, Sistema n dimensiones, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Temps retard, Delay time, Tiempo retardo, Interconnect sizing and spacing, and Power-delay optimization

Reduction of interconnect delay and interconnect power has become a primary design challenge in recent CMOS technology generations. Spacing between wires can be modified so that line-to-line capacitances will be optimized for minimal power under timing constraints. In this paper, we present a novel algorithm for simultaneous multilayer interconnect spacing that minimizes the total dynamic power dissipation caused by an interconnect, while maximum delay constraints are satisfied. A multidimensional visibility graph is used to represent the problem, and a layout partitioning technique is applied to solve the problem efficiently. The algorithm was evaluated on an industrial microprocessor designed using the 32 nm technology, and it achieved a 5-12% reduction in interconnect switching power.

Electrical engineering, Electrotechnique, Energy, Énergie, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Matériaux, Materials, Electroénergétique, Electrical power engineering, Conversion directe et accumulation d'énergie, Direct energy conversion and energy accumulation, Conversion électrochimique: piles et accumulateurs électrochimiques, piles à combustibles, Electrochemical conversion: primary and secondary batteries, fuel cells, Energie, Energy, Energie. Utilisation thermique des combustibles, Energy. Thermal use of fuels, Appareils de production et de conversion d'énergie: énergie thermique, énergie électrique, énergie mécanique, etc, Equipments for energy generation and conversion: thermal, electrical, mechanical energy, etc, Piles à combustible, Fuel cells, Acier inoxydable ferritique, Ferritic stainless steel, Acero inoxidable ferrítico, Composé ternaire, Ternary compound, Compuesto ternario, Cuivre Oxyde, Copper Oxides, Cobre Óxido, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Interconnexion, Interconnection, Interconexión, Manganèse Oxyde, Manganese Oxides, Manganeso Óxido, Matériau revêtement, Coating material, Material revestimiento, Pile combustible oxyde solide, Solid oxide fuel cell, Pila combustible oxido sólido, Revêtement, Coatings, Revestimiento, Spinelles, Spinels, Espinelas, Coating, Interconnect, and Spinel

To protect solid oxide fuel cells (SOFCs) from chromium poisoning and to improve area specific resistance (ASR), Cu1.3Mn1.7O4 is thermally grown on AISI 430 ferritic stainless steel. The samples are characterized by X-ray diffraction (XRD), field emission scanning electron microscopy equipped with energy dispersive spectroscopy (FESEM-EDS) and 4-probe ASR tests. The results show that the coating not only decreases the ASR considerably, but also acts as a barrier to mitigate the sub-scale growth and to prevent chromium migration through the coating and the cathode. The EDS analysis reveals that a mixed spinel region is formed between the coating and oxide scale after 500 h oxidation at 750 °C causing a noticeable decrease in oxygen diffusivity through this layer and subsequent decline in sub-scale growth rate. The ASR of uncoated sample is measured to be 63.5 mΩ cm2 after 500 h oxidation, while the Cu1.3Mn1.7O4 spinel coated sample shows a value of 19.3 mΩ cm2 representing ∼70% reduction compared to the uncoated sample. It is proposed that the high electrical conductivity of Cu1.3Mn1.7O4 (140 S cm-1), reduction of oxide scale growth, and good bonding between the coating and substrate contribute to the substantial ASR reduction for the coated sample.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Circuit séquentiel, Sequential circuit, Circuito secuencial, Circuit bistable, Flip-flop circuits, Circuit intégré, Integrated circuit, Circuito integrado, Consommation électricité, Electric power consumption, Consumo electricidad, Diaphonie, Crosstalk, Diafonía, Economies d'énergie, Energy savings, Ahorros energía, Electronique faible puissance, Low-power electronics, Gain, Ganancia, Horloge, Clock, Reloj, Interconnexion, Interconnection, Interconexión, Optimisation, Optimization, Optimización, Multi-bit flip-flop, Physical design, Power optimization, and Synthesis for low power

Applying multi-bit flip-flops (MBFFs) for clock power reduction in modern nanometer ICs has been becoming a promising lower-power design technique. Many previous works tried to utilize as more MBFFs with larger number of bits as possible to gain more clock power saving. However, an MBFF with larger number of bits may lead to serious crosstalk due to the close interconnecting wires belonging to different signal nets which are connected to the same MBFF. This paper analyzes, evaluates, and compares the relationship between power consumption and crosstalk when applying MBFFs with different numbers of bits. To solve the addressed problem, a novel crosstalk-aware power optimization approach is further proposed to optimize power consumption while satisfying the crosstalk constraint. Experimental results show that the proposed approach is very effective in crosstalk avoidance when applying MBFFs for power optimization.