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Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Instruments, appareillage, composants et techniques communs à plusieurs branches de la physique et de l'astronomie, Instruments, apparatus, components and techniques common to several branches of physics and astronomy, Techniques et équipements généraux, General equipment and techniques, Capteurs (chimiques, optiques, électriques, de mouvement, de gaz, etc.); télédétection, Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs à images, Imaging devices, Capteur image CMOS, CMOS image sensors, Capteur mesure, Measurement sensor, Captador medida, Carbone, Carbon, Carbono, Courant obscurité, Dark current, Corriente obscuridad, Détecteur image, Image sensor, Detector imagen, Evaluation performance, Performance evaluation, Evaluación prestación, Impureté, Impurity, Impureza, Qualité image, Image quality, Calidad imagen, Solution solide, Solid solution, Solución sólida, Sorption getter, Gettering, Spectrométrie transitoire niveau profond, Deep level transient spectrometry, Espectrometría transitoria nivel profundo, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, 0707D, Contamination, DLTS, and Image sensors

In complementary metal-oxide-semiconductor (CMOS) imager sensors, metallic contamination is a critical issue because it induces dark current and increases yield loss. Therefore, the challenge is to identify and eliminate progressively lower doses of metallic contamination. In recent years, Mo and W have received much attention because of their adverse effect on image sensor quality. This paper presents data from the testing of proximity gettering layers obtained by C or Si implantation, for what concerns their efficiency in Mo and W gettering. Deep-level transient spectroscopy (DLTS) was used to measure the impurity concentration in solid solution to evaluate gettering efficiency. Carbon implantation was found to be effective in capturing impurities, whereas Si implantation was not effective. Extended defects did not play a relevant role in gettering impurities, while gettering was found to be most effective in high impurity concentrations.

Crystallography, Cristallographie cristallogenèse, Electronics, Electronique, Metallurgy, welding, Métallurgie, soudage, Condensed state physics, Physique de l'état condensé, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Etat condense: structure electronique, proprietes electriques, magnetiques et optiques, Condensed matter: electronic structure, electrical, magnetic, and optical properties, Etats électroniques, Electron states, Méthodes de calcul de structure électronique, Methods of electronic structure calculations, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Dispositifs optoélectroniques, Optoelectronic devices, Bruit fond, Background noise, Ruido fondo, Capteur image CMOS, CMOS image sensors, Capteur image, Image sensors, Densité élevée, High density, Densidad elevada, Dopage, Doping, Dose, Dosis, Eclairement, Illumination, Alumbrado, Méthode fonctionnelle densité, Density functional method, Point fusion, Melting point, Punto fusión, Profil dopage, Doping profile, Perfil doping, Recuit faisceau laser, Laser beam annealing, Recuit thermique, Thermal annealing, Recocido térmico, Semiconducteur, Semiconductor materials, Semiconductor(material), 7115M, 8560J, BF2, CMOS image sensor, DFT, backside illumination, and backside junction

Backside illumination complementary metal oxide semiconductor image sensors (BSI CISs) represent an advanced technology that produces high-quality image sensors. However, BSI CISs are limited by high dark signals and noise signals on the backside. To address these problems, backside junctions are commonly used. High-dose backside junctions effectively reduce dark signals and noise signals. The depth of the implantation profile is a key factor in determining the junction depth. A laser thermal annealing process is conducted only near the surface to the activation, and thus broader doping profiles are limitations to be activation of dopants. Changing the dopant from B to BF2 can decrease the implant projected range. However, there are abnormal activation rates for BF2 in applications involving laser thermal annealing processes for shallow junctions. Although the need for BF2 is increasing, a mechanism for its slow activation and low activation rates has not yet been confirmed. Here, we identify the mechanism by which BF2 undergoes low activation after a melting threshold temperature and explain why this phenomenon occurs. In addition, we confirm a condition that provides high activation rates of BF2 and show the reduction of dark signals and noise signals at the high density BSI CISs.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Diodes, Transistors, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs à images, Imaging devices, Antenne imprimée, Printed antenna, Antena imprimida, Appareil portatif, Portable equipment, Aparato portátil, Architecture réseau, Network architecture, Arquitectura red, Capteur image CMOS, CMOS image sensors, Capteur mesure, Measurement sensor, Captador medida, Conception compacte, Compact design, Concepción compacta, Diode barrière Schottky, Schottky barrier diode, Diodo barrera Schottky, Domaine fréquence THz, THz range, Détecteur image, Image sensor, Detector imagen, Evaluation performance, Performance evaluation, Evaluación prestación, Fonction réponse, Response function, Función respuesta, Formation image, Imaging, Formación imagen, Imagerie onde submillimétrique, Submillimeter wave imaging, Imageur, Imager, Implémentation, Implementation, Implementación, Marché concurrentiel, Open market, Libre mercado, Réseau capteur, Sensor array, Red sensores, Réseau diode, Diode array, Red diodo, Silicium, Silicon, Silicio, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Technologie MOS, MOS technology, Tecnología MOS, Transistor MOSFET, MOSFET, 0707D, CMOS, NEP, detector, image sensor, imaging, lens-less, on-chip patch antenna, responsivity, and terahertz

Schottky-barrier diodes (SBD's) fabricated in CMOS without process modification are shown to be suitable for active THz imaging applications. Using a compact passive-pixel array architecture, a fully-integrated 280-GHz 4 × 4 imager is demonstrated. At 1-MHz input modulation frequency, the measured peak responsivity is 5.1 kV/W with ±20% variation among the pixels. The measured minimum NEP is 29 pW/Hz1/2. Additionally, an 860-GHz SBD detector is implemented by reducing the number of unit cells in the diode, and by exploiting the efficiency improvement of patch antenna with frequency. The measured NEP is 42 pW/Hz1/2 at 1-MHz modulation frequency. This is competitive to the best reported performance of MOSFET-based pixel measured without attaching an external silicon lens (66 pW/Hz1/2 at 1 THz and 40 pW/Hz1/2 at 650 GHz). Given that incorporating the 280-GHz detector into an array increased the NEP by ∼ 20%, the 860-GHz imager array should also have the similar NEP as that for an individual detector. The circuits were utilized in a setup that requires neither mirrors nor lenses to form THz images. These suggest that an affordable and portable fully-integrated CMOS THz imager is possible.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Essais, mesure, bruit et fiabilité, Testing, measurement, noise and reliability, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Dispositifs à images, Imaging devices, Appareillage essai, Testing equipment, Aparato ensayo, Bruit basse fréquence, 1/f noise, Ruido baja frecuencia, Bruit de télégraphe aléatoire, Random telegraph noise, Ruido telegráfico errático, Canal enterré, Buried channel, Canal enterrado, Capteur image CMOS, CMOS image sensors, Caractéristique statique, Static characteristic, Característica estática, Echelle grande, Large scale, Escala grande, Mesure bruit, Noise measurement, Méthode statistique, Statistical method, Método estadístico, Structure surface, Surface structure, Estructura superficie, Structure tunnel, Channel structure, Estructura túnel, Suiveur, Follower, Seguidor, Transistor, low-frequency noise, and noise measurement

Using a large-scale array test circuit, both static characteristics and random telegraph noise (RTN) of in-pixel source follower equivalent transistors of a CMOS image sensor with buried and surface channel transistor structures were statistically evaluated under various current and body bias conditions. The distribution of noise intensities at various operational bias conditions, correlations between RTN amplitude and static characteristics were analyzed. It was found that the RTN amplitude has a positive correlation between the subthreshold swing for both types of transistors.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Instruments, appareillage, composants et techniques communs à plusieurs branches de la physique et de l'astronomie, Instruments, apparatus, components and techniques common to several branches of physics and astronomy, Techniques et équipements généraux, General equipment and techniques, Capteurs (chimiques, optiques, électriques, de mouvement, de gaz, etc.); télédétection, Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Dispositifs à images, Imaging devices, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Bruit quantification, Quantization noise, Ruido cuantificación, Capteur image CMOS, CMOS image sensors, Capteur mesure, Measurement sensor, Captador medida, Conversion fréquence, Frequency conversion, Conversión frecuencia, Echantillonnage, Sampling, Muestreo, Implémentation, Implementation, Implementación, Miniaturisation, Miniaturization, Miniaturización, Modulation fréquence impulsion, Chirp modulation, Processeur 8 bits, 8 bit Processor, Procesador 8 bits, Rapport signal bruit, Signal to noise ratio, Relación señal ruido, Réponse dynamique, Dynamic response, Respuesta dinámica, Réseau porte programmable, Field programmable gate array, Red puerta programable, 0707D, -CMOS image sensor, dynamic range (DR), pulse-frequency-modulation (PFM) pixel, quad sampling, and signal-to-noise ratio (SNR)

We present a wide dynamic range (WDR) CMOS image sensor structure using the pulse-frequency modulation (PFM) pixel. The proposed pixel achieves a dynamic range (DR) of 124 dB with 8-bit resolution and operates in 60 frames/s. A quad-sampling technique is implemented that successfully reduces the pixel size by only using a 6-bit counter within the pixel. The sampling method incorporates cooperation between the pixel and column circuits to generate an automatically compressed signal that can be directly displayed without post-processing. This design has been verified through the field-programmable gate array (FPGA) implementation with a sample pixel. According to the experimental results, the sensor signal-to-noise ratio (SNR) is mainly limited by the quantization noise of the light-to-frequency conversion. The maximum SNR is 48 dB, and the common SNR dip is successfully avoided. In addition, the achievable array size is determined by all sampling periods and can be of megapixels with appropriate designs.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs à images, Imaging devices, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Amplificateurs, Amplifiers, Circuits analogiques, Analog circuits, Circuit intégré, Integrated circuit, Circuito integrado, Amplificateur, Amplifier, Amplificador, Capteur image CMOS, CMOS image sensors, Circuit LSI, LSI circuit, Circuito LSI, Circuit analogique, Analog circuit, Circuito analógico, Circuit faible bruit, Low noise circuit, Circuito débil ruido, Conception circuit intégré, Integrated circuit design, Détecteur de gaz, Gas detector, Detector de gas, Détecteur particule, Particle detector, Detector partícula, Détecteur semiconducteur, Semiconductor detector, Detector semiconductor, Electronique de mesure, Readout electronics, Etalonnage, Calibration, Contraste, Evaluation performance, Performance evaluation, Evaluación prestación, Gain, Ganancia, Mesure charge électrique, Charge measurement, Programme SPICE, SPICE, Préamplificateur, Preamplifier, Preamplificador, Réponse dynamique, Dynamic response, Respuesta dinámica, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, 0707D, analog circuit, charge-sensitive amplifier, high-dynamic, low-noise, particle detector, and pixel readout LSI

Recent attempts to directly combine CMOS pixel readout chips with modern gas detectors open the possibility to fully take advantage of gas detectors. Those conventional readout LSIs designed for hybrid semiconductor detectors show some issues when applied to gas detectors. Several new proposed readout LSIs can improve the time and the charge measurement precision. However, the widely used basic charge sensitive amplifier (CSA) has an almost fixed dynamic range. There is a trade-off between the charge measurement resolution and the detectable input charge range. This paper presents a method to apply the folding integration technique to a basic CSA. As a result, the detectable input charge dynamic range is expanded while maintaining all the key merits of a basic CSA. Although folding integration technique has already been successfully applied in CMOS image sensors, the working conditions and the signal characteristics are quite different for pixel readout LSIs for gas particle detectors. The related issues of the folding CSA for pixel readout LSIs, including the charge error due to finite gain of the preamplifier, the calibration method of charge error, and the dynamic range expanding efficiency, are addressed and analyzed. As a design example, this paper also demonstrates the application of the folding integration technique to a Qpix readout chip. This improves the charge measurement resolution and expands the detectable input dynamic range while maintaining all the key features. Calculations with SPICE simulations show that the dynamic range can be improved by 12dB while the charge measurement resolution is improved by 10 times. The charge error during the folding operation can be corrected to less than 0.5%, which is sufficient for large input charge measurement.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Dispositifs à images, Imaging devices, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Amplificateurs, Amplifiers, Réseaux neuronaux, Neural networks, Composé II-VI, II-VI compound, Compuesto II-VI, Amplificateur, Amplifier, Amplificador, Bruit grenaille, Shot noise, Ruido granalla, Capteur image CMOS, CMOS image sensors, Circuit faible bruit, Low noise circuit, Circuito débil ruido, Consommation électricité, Electric power consumption, Consumo electricidad, Conversion AN, AD conversion, Conversión AN, Détecteur image, Image sensor, Detector imagen, Echantillonnage, Sampling, Muestreo, Electronique de mesure, Readout electronics, Etude comparative, Comparative study, Estudio comparativo, Faisabilité, Feasibility, Practicabilidad, Gain, Ganancia, Mesure de distance, Distance measurement, Medición distancia, Mode courant, Current mode, Modo corriente, Méthode Monte Carlo, Monte Carlo method, Método Monte Carlo, Méthode adaptative, Adaptive method, Método adaptativo, Rapport signal bruit, Signal to noise ratio, Relación señal ruido, Réponse dynamique, Dynamic response, Respuesta dinámica, Réseau neuronal flou, Fuzzy neural nets, Simulation numérique, Numerical simulation, Simulación numérica, Sulfure de cadmium, Cadmium sulfide, Cadmio sulfuro, CdS, Correlated double sampling (CDS) comparison, digital correlated multiple sampling (DCMS), fixed pattern noise (FPN), gain-adaptive amplifier, and wide dynamic range (DR) image sensors

A robust gain-adaptive column amplifier scheme, which is friendly to the digital correlated multiple sampling (DCMS) A/D conversion is proposed to extend the dynamic range of CMOS image sensors. It lowers the noise at low light levels and relaxes the gain to prevent saturation at high light levels, while a low-noise readout circuit is not necessary because of the dominance of photon shot noise. Since the difference between the reset and the signal levels at a 4-T pixel output is compared with reference voltages to detect the suitable gain values, the fixed pattern noise (FPN) caused by this gain-detection scheme is estimated to be 20 times lower than that of the work in which only the pixel signal level is compared. Operation analysis and Monte Carlo simulations show the immunity of the circuit to unwanted offsets. Noise analysis and SNR calculation show that the FPN by the gain-detection scheme is more suppressed with either more gain options or the DCMS conversion applied at the amplifier output. A column-level design with a size of 9 × 500 μm and a current consumption of 12 μA is discussed to demonstrate the feasibility of the idea.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Essais, mesure, bruit et fiabilité, Testing, measurement, noise and reliability, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Dispositifs à images, Imaging devices, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Amplificateurs, Amplifiers, Amplificateur, Amplifier, Amplificador, Autotest, Built in self test, Autoprueba, Capteur image CMOS, CMOS image sensors, Conception modulaire, Modular design, Concepción modular, Décodage, Decoding, Desciframiento, Electronique de mesure, Readout electronics, Empilement, Stacking, Apilamiento, Evaluation performance, Performance evaluation, Evaluación prestación, Formation image, Imaging, Formación imagen, Haute résolution, High resolution, Alta resolucion, Imageur, Imager, Modèle 2 dimensions, Two dimensional model, Modelo 2 dimensiones, Modèle 3 dimensions, Three dimensional model, Modelo 3 dimensiones, Photographie rapide, High speed photography, Fotografía rápida, Résolution spatiale, Spatial resolution, Resolución espacial, Système commande, Control system, Sistema control, Transistor, Télévision haute résolution, High definition television, Televisión alta definición, 3-D ICs, BIST, high frame rate, micro-bump, and sharing floating diffusion amplifier

This paper presents a 3 megapixel 100 fps 2.8 μm pixel pitch CMOS image sensor (CIS) layer with built-in self-test (BIST) for three-dimensional (3D) integrated imagers. A modular CIS sub-array is proposed with new readout and control scheme. It needs only one micro-bump (μbump) per sub-array, instead of per-pixel or per-column, to release the design rule restriction of the 3D stacking process. The proposed readout structure with in-pixel two-dimensional (2D) decoding function achieves high spatial resolution, without degrading the frame rate. A BIST circuit is also proposed to filter out unqualified CIS layer before chip stacking, improving the yield performance of the final 3D integrated imagers, without adding extra transistor in the pixel. A CIS chip with 16 × 8 sub-arrays and a pixel size of 2.8 x 2.8 μm2 was fabricated in TSMC 0.18 μm CIS process. The experimental results demonstrate the successful parallel output images of 3 megapixels with 16 × 8 modules at 100 fps. This shows that the imaging resolution is expandable by the proposed modular sub-array design and is expected to achieve 100 fps at multi-mega imaging for high-speed HDTV camera applications.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs à images, Imaging devices, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Convertisseurs de signal, Signal convertors, Capteur image CMOS, CMOS image sensors, Consommation électricité, Electric power consumption, Consumo electricidad, Convertisseur courant, Power convertor, Convertidor corriente, Eclairement, Illumination, Alumbrado, Electronique faible puissance, Low-power electronics, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Facteur remplissage, Fill factor, Gain, Ganancia, Haute résolution, High resolution, Alta resolucion, Imageur, Imager, Implémentation, Implementation, Implementación, Industrie électronique, Electronics industry, Industria electrónica, Mode courant, Current mode, Modo corriente, Multiplexage, Multiplexing, Multiplaje, Optimisation, Optimization, Optimización, Prototype, Prototipo, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Artificial retina, CMOS image sensor (CIS), programming (PG) mode and implanted (IP) mode, and sense-and-stimulus (SAS) pixel

This paper presents a 0.8-V CMOS imager with 4096 pixels and an integrated sense-and-stimulus (SAS) function for retinal prosthesis. The pixel consists of a photon-to-biphasic-current converter (sense) and a balanced current-mode stimulator (stimulus) to achieve a highly integrated and low-power solution for high-resolution vision recovery. Three operation modes, that is, test mode, programming (PG) mode, and implanted (IP) mode, have been implemented for various purposes. In test mode, the internal signals are multiplexed out serially for chip verification. In PG mode, the output pattern of the current stimulator array is programmable by external addresses for patterned electrical stimulus experiments of retina. In IP mode, the chip is fully functional with a minimized number of input/output as four optimized for in vivo operation. A prototype chip with a 64 x 64 SAS-pixel array, a 30 × 30 μm2 pixel size, and a 33.3% fill factor was designed and fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm CMOS image sensor technology. The proposed chip was operational under a wide supply range from 0.8 to 1.8 V. The measured conversion gains and maximal biphasic current amplitudes are 144 nA/lx (1.8 V), 21 nA/lx (0.8 V), ±50 μA (1.8 V), and ±10 μA (0.8 V), respectively. The proposed SAS CMOS imager presents an integrated SAS solution for artificial retina with the highest array resolution of 4096 pixels and a low power consumption of 0.18 mW at 12.5 ft/s and a 0.8-V supply under 300-lx illumination.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Instruments, appareillage, composants et techniques communs à plusieurs branches de la physique et de l'astronomie, Instruments, apparatus, components and techniques common to several branches of physics and astronomy, Techniques et équipements généraux, General equipment and techniques, Capteurs (chimiques, optiques, électriques, de mouvement, de gaz, etc.); télédétection, Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs à images, Imaging devices, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Réseaux neuronaux, Neural networks, Bruit aléatoire, Random noise, Ruido aleatorio, Capteur image CMOS, CMOS image sensors, Capteur mesure, Measurement sensor, Captador medida, Commande courant, Current control, Control corriente, Implémentation, Implementation, Implementación, Modulation durée impulsion, Pulse duration modulation, Modulación duración impulsos, Prototype, Prototipo, Réponse dynamique, Dynamic response, Respuesta dinámica, Réseau neuronal flou, Fuzzy neural nets, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, 0707D, Ultra-basse tension, Ultralow voltage, CMOS imager, dynamic range, fixed-pattern-noise (FPN), and pulse-width modulation (PWM)

This paper presents a 0.5 V operated pulse-width modulation (PWM) CMOS imager with threshold-variation canceling (TVC) and programmable current-controlled threshold (PCCT) schemes implemented in 0.18 μm CMOS technology. The proposed TVC scheme efficiently improves the fixed-pattern-noise (FPN) issue caused by process variation in conventional PWM sensors. The limited dynamic range in ultra-low-voltage operated sensor can be extended by 56.5 dB with the proposed PCCT operation. The measurement results of the prototype chip show an array FPN of 0.055%, a column FPN of 0.016%, a dark random noise of 0.65 LSB, and a dynamic range (DR)of 82 dB. The total chip consumes 4.95 uW and 29.6 μW at 11.8 fps and 78.5 fps, which achieves an iFOM of 163.9 pW/f-p and 147.3 pW/f-p, respectively.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Dispositifs diélectriques et dispositifs à base de verre et de solides amorphes, Dielectric, amorphous and glass solid devices, Dispositifs optoélectroniques, Optoelectronic devices, Dispositifs à images, Imaging devices, Energie, Energy, Energie naturelle, Natural energy, Energie solaire, Solar energy, Conversion photovoltaïque, Photovoltaic conversion, Cellules solaires. Cellules photoélectrochimiques, Solar cells. Photoelectrochemical cells, Accumulation énergie, Energy storage, Acumulación energía, Capacité commutée, Switched capacity, Capacidad conmutada, Capacité électrique, Capacitance, Capacitancia, Capteur image CMOS, CMOS image sensors, Cellule solaire, Solar cell, Célula solar, Circuit capacité commutée, Switched capacitor networks, Circuit intégré, Integrated circuit, Circuito integrado, Circuit logique CMOS, CMOS logic circuits, Condensateur, Capacitor, Condensador, Convertisseur courant continu, Direct current convertor, Convertidor corriente continua, Etude comparative, Comparative study, Estudio comparativo, Evaluation performance, Performance evaluation, Evaluación prestación, Illumination hors axe, Off axis illumination, Iluminación fuera de eje, Implémentation, Implementation, Implementación, Interconnexion, Interconnection, Interconexión, Matrice formage, Die, Matriz formadora, Photodiode, Fotodiodo, Récupération énergie, Energy recovery, Recuperación energía, Réseau diffraction, Diffraction grating, Rejilla difracción, Réseau diode, Diode array, Red diodo, Tension sortie, Output voltage, Voltage salida, Télécommunication sans fil, Wireless telecommunication, Telecomunicación sin hilo, 4279D, energy-harvesting, implantable biomedical device, integrated storage, low power, and photodiode

Integrating energy-harvesting photodiodes with logic and exploiting on-die interconnect capacitance for energy storage can enable new, ultraminiaturized wireless systems. Unlike CMOS imager pixels, the proposed photodiode designs utilize p-diffusion fingers and are implemented in a conventional logic process. Also unlike specialized solar cell processes, the designs utilize the on-chip metal interconnect to form a diffraction grating above the p-diffusion fingers which also provides capacitive energy storage. To explore the tradeoffs between optical efficiency and energy storage for integrated photodiodes, an array of photovoltaics with various diffractive storage capacitors was designed in a 90-nm CMOS logic process. The diffractive effects can be exploited to increase the photodiodes' response to off-axis illumination. Transient effects from interfacing the photodiodes with switched-capacitor DC―DC converters were examined, with measurements indicating a 50% reduction in the output voltage ripple due to the diffractive storage capacitance. A quantitative comparison between 90-nm and 0.35-μm CMOS logic processes for energy-harvesting capabilities was carried out. Measurements show an increase in power generation for the newer CMOS technology, however at the cost of reduced output voltage. One potential application for the integrated photodiodes is harvesting energy for a subdermal biomedical device.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Généralités (incluant les aspects économiques et industriels), General (including economical and industrial fields), Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs à images, Imaging devices, Apprentissage, Learning, Aprendizaje, Capteur image CMOS, CMOS image sensors, Circuit intégré CMOS, CMOS integrated circuits, Densité défaut, Defect density, Densidad defecto, Formation image, Imaging, Formación imagen, Industrie électronique, Electronics industry, Industria electrónica, Modélisation, Modeling, Modelización, Mécanisme croissance, Growth mechanism, Mecanismo crecimiento, Série temporelle, Time series, Serie temporal, forecasting, imaging, modelling, and yield estimation

This paper presents a novel approach to modeling yield using the Gompertz function, which is widely used in biology to model the growth processes of plants, tumors, etc. We demonstrate that the yield-learning process in a semiconductor fab follows the same behavior of the growth of biological systems. We start with a simple time series model, which describes the learning process in terms of defect density reduction. Then we obtain the Gompertz growth model, which also fits the experimental data better than more traditional learning models such as the Gruber's general yield learning model [38].

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs optoélectroniques, Optoelectronic devices, Dispositifs à images, Imaging devices, Dispositif optoélectronique, Optoelectronic device, Dispositivo optoelectrónico, Capteur image CMOS, CMOS image sensors, Courant photoélectrique, Photoelectric current, Corriente fotoeléctrica, Détecteur image, Image sensor, Detector imagen, Mesure de distance, Distance measurement, Medición distancia, Photodiode, Fotodiodo, Pixel intelligent, Smart pixels, Réduction bruit, Noise reduction, Reducción ruido, Réponse dynamique, Dynamic response, Respuesta dinámica, Réseau neuronal flou, Fuzzy neural nets, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Technologie MOS, MOS technology, Tecnología MOS, Transistor MOSFET, MOSFET, Active pixel sensor, CMOS image sensors (CISs), fixed pattern noise (FPN), and wide dynamic range (WDR)

A 100 x 98 CMOS image sensor (CIS) fabricated in a standard 0.35-μm CMOS technology is described. The pixels in this CIS integrate the photocurrent in each pixel for a time that depends upon the photocurrent to map wide-dynamic-range (WDR) real-world scenes to a lower DR output. To improve their low-light sensitivity, these pixels include a MOSFET that restricts the voltage changes on the photodiode. In addition, the user-defined input voltage needed to generate a WDR response is one that preserves the low-light sensitivity of the pixels. This results in pixels with a linear response at low photocurrents and a logarithmic response at larger photocurrents. Results are presented, which show that a fixed-pattern-noise (FPN) correction procedure based upon assuming either a linear or a logarithmic response introduces artifacts into some images. An FPN correction procedure that both avoids these artifacts and accurately estimates the mean photocurrent in the array is then presented.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs à transfert de charge, Charge transfer devices, Dispositifs optoélectroniques, Optoelectronic devices, Dispositifs à images, Imaging devices, Dispositif optoélectronique, Optoelectronic device, Dispositivo optoelectrónico, Boucle anticipation, Feedforward, Ciclo anticipación, Capteur image CMOS, CMOS image sensors, Dispositif CCD, Charge coupled device, Dispositivo carga acoplada, Détecteur image, Image sensor, Detector imagen, Electronique de mesure, Readout electronics, Emission thermoionique, Thermionic emission, Emisión termoiónica, Hauteur barrière, Barrier height, Altura barrera, Imageur, Imager, Photodiode, Fotodiodo, Puits potentiel, Potential well, Pozo potencial, Réponse dynamique, Dynamic response, Respuesta dinámica, Résolution spatiale, Spatial resolution, Resolución espacial, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Transfert charge, Charge transfer, Transferencia carga, CMOS image sensor, charge transfer, feedforward voltage, and pinned photodiode (PPD)

The charge handling capacity or the full well of the photodiodes used in CMOS image sensors is a very important characteristic because it affects the saturation level and the dynamic range of the image sensor. The scaling of the pixel size to increase the spatial resolution is also reducing the barrier separating the photon detection and the collection node in a standard pinned photodiode (PPD). The barrier reduction and the thermionic emission of the electrons allow some of the charges from the photodiode well to feed into the collection node, resulting in a feedforward voltage. In conventional readout of the pixels, this feedforward voltage is neglected and lost when the collection node is reset. The barrier height of the transfer gate (TG) determines the quantity of electrons held back in the photodiode well. Thus, the knowledge of this barrier height is very important in determining the true charge handling capacity of the photodiode potential well. Experiments with standard PPDs showed that a barrier height of around 0.5 V is needed to hold the electrons in the photodiode potential well. This is analogous to the barrier potential for charge-coupled devices reported in the literature. Furthermore, the barrier height dependence on the charge storing time in the photodiode well and the structural dimensions of the TG and photodiode length are also explored in this paper.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Instruments, appareillage, composants et techniques communs à plusieurs branches de la physique et de l'astronomie, Instruments, apparatus, components and techniques common to several branches of physics and astronomy, Techniques et équipements généraux, General equipment and techniques, Capteurs (chimiques, optiques, électriques, de mouvement, de gaz, etc.); télédétection, Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Dispositifs à images, Imaging devices, Accumulation charge, Charge accumulation, Acumulación carga, Capteur image CMOS, CMOS image sensors, Capteur mesure, Measurement sensor, Captador medida, Circuit séparateur, Separator circuit, Circuito separador, Détecteur image, Image sensor, Detector imagen, Détection changement, Change detection, Detección cambio, Evaluation performance, Performance evaluation, Evaluación prestación, Excitateur, Driver, Excitador, Formation image, Imaging, Formación imagen, Haute performance, High performance, Alto rendimiento, Hydrogène, Hydrogen, Hidrógeno, Miniaturisation, Miniaturization, Miniaturización, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Réaction chimique, Chemical reaction, Reacción química, Transfert charge, Charge transfer, Transferencia carga, 0707D, CMOS image sensor, Photo, charge transfer technique, chemical reaction, pH, and real-time imaging

The charge transfer technique, which is capable of operating in charge accumulation-mode, is suitable for use in pH-imaging to detect small changes in potential. An advanced charge-transfer-type hydrogen ion image sensor consisting of 128 × 128 pixels with a 23- μm pixel pitch is fabricated. A new scanning system and high-performance drive buffer circuits are adopted to achieve high frame rates. For miniaturization of the sensor pixels, we developed an advanced new fabrication process. The pH sensitivity is 32.8 mV/pH when using standard pH solutions. Videos of the movement of hydrogen ions are clearly obtained with the 128 × 128 pixels display, and photo images are taken simultaneously with the videos of the movement of hydrogen ions. A frame rate of 58 frames per second is realized with this image sensor.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Instruments, appareillage, composants et techniques communs à plusieurs branches de la physique et de l'astronomie, Instruments, apparatus, components and techniques common to several branches of physics and astronomy, Techniques et équipements généraux, General equipment and techniques, Capteurs (chimiques, optiques, électriques, de mouvement, de gaz, etc.); télédétection, Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs à images, Imaging devices, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Convertisseurs de signal, Signal convertors, Assemblage circuit intégré, Integrated circuit bonding, Capteur image CMOS, CMOS image sensors, Capteur mesure, Measurement sensor, Captador medida, Circuit intégré, Integrated circuit, Circuito integrado, Contact bosse, Solder bump, Contacto con bollos, Convertisseur AN, AD converter, Convertidor AN, Cuivre, Copper, Cobre, Echantillonnage, Sampling, Muestreo, Empilement, Stacking, Apilamiento, Haute performance, High performance, Alto rendimiento, Image tridimensionnelle, Tridimensional image, Imagen tridimensional, Interconnexion, Interconnection, Interconexión, Matrice formage, Die, Matriz formadora, Multifonctionnalité, Multifunctionality, Multifuncionalidad, Prototypage rapide, Rapid prototyping, Prototipificación rápida, Prototype, Prototipo, Silicium, Silicon, Silicio, Structure 3 dimensions, Three dimensional structure, Estructura 3 dimensiones, Surface arrière, Back surface, Superficie atrás, Système intégré, Integrated system, Sistema integrado, Trou interconnexion, Via hole, Agujero interconexión, 0707D, Backside through silicon via (TSV), die-level 3-D integration, and hetero-integrated system

We proposed a die-level 3-D integration technology for rapid prototyping of high-performance multifunctionality hetero-integrated systems. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die level. To realize the die-level 3-D integration, fine-sized backside through silicon via (TSV) and novel detachable technologies are developed. In this paper, we demonstrated a prototype 3-D stacked image sensor system using the die-level 3-D integration technology. Three different functional chips of CMOS image sensor, correlated double sampling, and analog-to-digital converter, which were fabricated by different technologies, were processed to form fine-sized backside Cu TSV of 5-μm diameter and metal microbumps in die level. Each chip was sequentially stacked after evaluating the basic function to form a known-good-die 3-D stacked system. The fundamental characteristics of each functional chip were successfully evaluated in the fabricated prototype 3-D stacked image sensor system.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs optoélectroniques, Optoelectronic devices, Dispositifs à images, Imaging devices, Dispositif optoélectronique, Optoelectronic device, Dispositivo optoelectrónico, Capteur image CMOS, CMOS image sensors, Conception assistée, Computer aided design, Concepción asistida, Conception circuit, Circuit design, Diseño circuito, Durabilité, Durability, Durabilidad, Durée vie porteur charge, Carrier lifetime, Etude comparative, Comparative study, Estudio comparativo, Fiabilité, Reliability, Fiabilidad, Méthode analytique, Analytical method, Método analítico, Photodiode, Fotodiodo, Porteur minoritaire, Minority carrier, Portador minoritario, Silicium, Silicon, Silicio, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Tension circuit ouvert, Open circuit voltage, Lifetime, Simulation, and TCAD

The control and prediction of minority carrier lifetime are crucial for the design of photodiodes, especially for CMOS image sensors, because signal electrons must be captured before recombination. Analytic models have been developed but do not allow accurate and reliable lifetime estimations according to complex photodiode architecture. In this work, we show for the first time that mixed-mode TCAD simulations produce accurate and reliable results for realistic photodiode designs. To arrive at this conclusion, we have performed measurements and simulations on two different photodiodes using the Open Circuit Voltage Decay method.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs optoélectroniques, Optoelectronic devices, Dispositifs à images, Imaging devices, Dispositif optoélectronique, Optoelectronic device, Dispositivo optoelectrónico, Capteur image CMOS, CMOS image sensors, Conception optimale, Optimal design, Concepción optimal, Courant photoélectrique, Photoelectric current, Corriente fotoeléctrica, Diaphonie, Crosstalk, Diafonía, Eclairement, Illumination, Alumbrado, Haute résolution, High resolution, Alta resolucion, Miniaturisation, Miniaturization, Miniaturización, Modélisation, Modeling, Modelización, Méthode analytique, Analytical method, Método analítico, Paramètre géométrique, Geometrical parameter, Parámetro geométrico, Photodiode, Fotodiodo, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Crosstalk (CTK), modeling, photodiodes (PDs), and simulation

A closed-form and explicit 2-D analytical model for crosstalk (CTK) effects in p-n+ CMOS photodiodes for pixel design optimization has been developed in this paper. This model complements and extends a previous development describing the photocurrent because of the active area illumination along with the lateral depletion region and lateral components owing to the diffused photocarriers from the surroundings of the junction. The model has very few fitting parameters because it is physically based. Similarly, it can be of great use for CMOS image sensors designers, especially to fulfill high resolution and small area requirements by pixel size reduction. The model was validated extensively through device simulations with ATLAS and experimental data, and describes the CTK dependencies on light conditions and physical, geometrical, and process parameters.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Instruments, appareillage, composants et techniques communs à plusieurs branches de la physique et de l'astronomie, Instruments, apparatus, components and techniques common to several branches of physics and astronomy, Techniques et équipements généraux, General equipment and techniques, Capteurs (chimiques, optiques, électriques, de mouvement, de gaz, etc.); télédétection, Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs à images, Imaging devices, Appareillage embarqué, On board equipment, Equipo embarcado, Capteur image CMOS, CMOS image sensors, Capteur mesure, Measurement sensor, Captador medida, Caractéristique fonctionnement, Performance characteristic, Característica funcionamiento, Critère performance, Performance requirement, Criterio resultado, Détecteur image, Image sensor, Detector imagen, Etalonnage, Calibration, Contraste, Evaluation performance, Performance evaluation, Evaluación prestación, Imageur, Imager, Pixel intelligent, Smart pixels, Prototype, Prototipo, Rayonnement UV extrême, Vacuum ultraviolet radiation, Radiación ultravioleta extrema, Surface arrière, Back surface, Superficie atrás, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, 0707D, and space technology

For the Extreme Ultraviolet Imager (EUI) of the Solar Orbiter mission, to be launched in 2017, CMOS active pixel sensor (APS) prototypes have been developed with several test pixel designs. A set of measurements was carried out to evaluate their performance characteristics in visible and in extreme ultraviolet wavelengths. We present the results of measurement campaigns that lead to the selection of a preferred pixel design in regard to the scientific performance requirements of the EUI flight model detectors, i.e., back-thinned CMOS APS devices of 2048 x 2048 and 3072 x 3072 pixel formats with a 10-μm pixel pitch.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Dispositifs à images, Imaging devices, Bruit de télégraphe aléatoire, Random telegraph noise, Ruido telegráfico errático, Capteur image CMOS, CMOS image sensors, Histogramme, Histogram, Histograma, Intégration numérique, Numerical integration, Integración numérica, Loi normale, Gaussian distribution, Curva Gauss, Modèle statistique, Statistical model, Modelo estadístico, Méthode domaine temps, Time domain method, Método dominio tiempo, Temps retard, Delay time, Tiempo retardo, Valeur moyenne, Mean value, and Valor medio

A statistical model based on large sample simulation is established to study the relationship between random telegraph signal (RTS) noise and the number of time delay integration (TDI) stages in TDI CMOS image sensor (CIS). Matlab simulation results show that the mean value of RTS noise increases by a factor greater than M0.5 when the number of TDI stages is M, and the factor approximates to M0.5 with larger TDI stages. In noise histogram, RTS noise exhibits Gaussian distribution when the number of TDI stages is more than a special value. These results serve as a guideline for the design of TDI stages and the analysis of noise.