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Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Instruments, appareillage, composants et techniques communs à plusieurs branches de la physique et de l'astronomie, Instruments, apparatus, components and techniques common to several branches of physics and astronomy, Techniques, équipements et instruments mécaniques, Mechanical instruments, equipment and techniques, Systèmes et dispositifs micromécaniques, Micromechanical devices and systems, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs micro- et nanoélectromécaniques (mems/nems), Micro- and nanoelectromechanical devices (mems/nems), Metaux. Metallurgie, Metals. Metallurgy, Propriétés mécaniques. Rhéologie. Mécanique de la rupture. Tribologie, Mechanical properties and methods of testing. Rheology. Fracture mechanics. Tribology, Rupture, Fractures, Acide fluorhydrique, Hydrofluoric acid, Ácido fluorhídrico, Flusssaeure, Attaque chimique, Chemical etching, Ataque químico, Chemisches Aetzen, Capteur vibration, Vibration transducer, Transductor vibración, Cavité, Cavity, Cavidad, Circuit intégré, Integrated circuit, Circuito integrado, Integrierte Schaltung, Compatibilité, Compatibility, Compatibilidad, Kompatibilitaet, Couche mince, Thin film, Capa fina, Duennschicht, Couche sacrificielle, Sacrificial layer, Capa sacrificial, Dispositif microélectromécanique, Microelectromechanical device, Dispositivo microelectromecánico, Dispositif piézorésistif, Piezoresistive device, Dispositivo piezoresistivo, Endommagement, Damaging, Deterioración, Epaisseur, Thickness, Espesor, Dicke, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Gravure ionique réactive, Reactive ion etching, Grabado iónico reactivo, Gravure plasma, Plasma etching, Grabado plasma, Gravure sèche, Dry etching, Grabado seco, Interconnexion, Interconnection, Interconexión, Matériau amorphe, Amorphous material, Material amorfo, Micromachine, Micromáquina, Oxyde de silicium, Silicon oxides, Passivation, Pasivación, Passivierung, Pastille électronique, Wafer, Pastilla electrónica, Polymère fluor, Fluorine containing polymer, Polímero flúor, Procédé voie humide, Wet process, Procedimiento vía húmeda, Rendement élevé, High efficiency, Rendimiento elevado, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Technologie silicium sur isolant, Silicon on insulator technology, Tecnología silicio sobre aislante, Trou interconnexion, Via hole, Agujero interconexión, Uniformité, Uniformity, Uniformidad, Vibromètre, Vibrometer, Vibrómetro, 0707D, 8540H, SiO2, Cavity-first, Flexible fabrication, MEMS, Monolithic integration, Refilling, and Vapour-phase HF etching

This paper reports a novel cavity-first approach for producing released MEMS from front side of the silicon on insulator (SOI) wafer. This approach eliminates the requirements to sacrificial layer or wet chemical etching, avoids the damage to other components by vapour-phase HF dry etching, and exhibits excellent compatibility to CMOS. In this approach, prior to metal or SiO2 passivation layer deposition, cavities were formed by using vapour-phase hydrofluoric (HF) acid dry etching to remove SiO2 box layer through release holes with a diameter of a few micrometers, and then an amorphous fluoropolymer thin film was used to re-fill release holes without entering into the cavities. After other processes, MEMS structure can be finally released by inductive coupled plasma reactive ion etching (ICP-RIE) from front side of the wafer. To present the process details and its unique merits, i.e. high efficiency, better thickness uniformity in device layer, and less proof mass loss, a piezoresistive planer MEMS vibration sensor was fabricated by using above approach and its performance was evaluated. The results demonstrated that this approach is considerably valuable to both MEMS flexible fabrication and MEMS-CMOS monolithic integration.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Domaines interdisciplinaires: science des materiaux; rheologie, Cross-disciplinary physics: materials science; rheology, Science des matériaux, Materials science, Méthodes de dépôt de films et de revêtements; croissance de films et épitaxie, Methods of deposition of films and coatings; film growth and epitaxy, Electrodépôt, Electrodeposition, electroplating, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Analyse paramétrique, Parametric analysis, Analyse thermique, Thermal analysis, Análisis térmico, Caractéristique thermique, Thermal characteristic, Característica térmica, Circuit intégré, Integrated circuit, Circuito integrado, Compatibilité électromagnétique, Electromagnetic compatibility, Compatibilidad electromagnética, Conduction thermique, Thermal conduction, Conducción térmica, Conductivité thermique, Thermal conductivity, Conductividad térmica, Cuivre, Copper, Cobre, Dissipation thermique, Thermal dissipation, Disipación térmica, Dépôt électrolytique, Electrodeposition, Depósito electrolítico, Encapsulation plastique, Plastic packaging, Encapsulación plástica, Etude sur modèle, Model study, Estudio sobre modelo, Evaluation performance, Performance evaluation, Evaluación prestación, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Interconnexion, Interconnection, Interconexión, Matériau orthotrope, Orthotropic material, Material ortotropo, Packaging électronique, Electronic packaging, Packaging electrónico, Silicium, Silicon, Silicio, Transfert chaleur, Heat transfer, Transferencia térmica, Trou interconnexion, Via hole, Agujero interconexión, and 8115P

The effective model for the orthotropic TSV (Through Silicon Via) interposer in heat conduction for 2.5D IC integration was proposed in this study. The simple parallel model was used in out-of-plane direction to predict the effective thermal conductivity for the TSV interposer. The in-plane effective thermal conductivity for the interposer was derived on basis of heat balances. By introducing the effective orthotropic thermal parameters, the TSV structures can be ignored in the present effective model. The computations using the effective model for TSV interposer and the 2.5D package with interposer were carried out. The results showed that the accuracy of the effective model was above 95% comparing with the real model including TSV structures when the volume ratio of the electroplating copper and the silicon interposer is smaller than 10%. Using the effective model, the parametric studies on the interposer sizes and the thermal conductivities of different materials in the 2.5D package were conducted with higher efficiency. The results showed that the performance and sizes of EMC (Epoxy Molding Compound) and the package substrate are more important than that of internal underfills in heat dissipation of the package with TSV interposer.

Crystallography, Cristallographie cristallogenèse, Electronics, Electronique, Metallurgy, welding, Métallurgie, soudage, Condensed state physics, Physique de l'état condensé, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Instruments, appareillage, composants et techniques communs à plusieurs branches de la physique et de l'astronomie, Instruments, apparatus, components and techniques common to several branches of physics and astronomy, Techniques, équipements et instruments mécaniques, Mechanical instruments, equipment and techniques, Instrumentation pour déformation, force et couple, Instruments for strain, force and torque, Sciences appliquees, Applied sciences, Metaux. Metallurgie, Metals. Metallurgy, Contrôle, Analysing. Testing. Standards, Analyse des contraintes, Stress analysis, Analyse contrainte, Stress analysis, Análisis tensión, Spannungsanalyse, Analyse thermique, Thermal analysis, Análisis térmico, Thermische Analyse, Circuit intégré, Integrated circuit, Circuito integrado, Integrierte Schaltung, Coefficient dilatation thermique, Thermal expansion coefficient, Coeficiente dilatación térmica, Thermischer Ausdehnungskoeffizient, Contrainte thermique, Thermal stress, Tensión térmica, Waermespannung, Effet contrainte, Stress effects, Etude théorique, Theoretical study, Estudio teórico, Theoretische Untersuchung, Microstructure, Microestructura, Mikrogefuege, Modélisation, Modeling, Modelización, Méthode paramétrique, Parametric method, Método paramétrico, Méthode statistique, Statistical method, Método estadístico, Méthode élément fini, Finite element method, Método elemento finito, Finite Element Methode, Trou interconnexion, Via hole, Agujero interconexión, 0710P, IC integration, TSV interposer, finite-element analysis, modeling, and thermal stress

The thermal stress of typical integrated circuit (IC) integration with the interposer of through silicon via (TSV) was investigated in this study. To overcome the huge computational costs due to meshing the large amount of TSVs' microstructures, a simplified method, i.e. the complement sector model, was proposed and verified by the symmetric 1/8th full model. Using the sector model, the parametric studies were carried out to reveal the critical locations of TSV and the crucial parameters. Furthermore, statistical methods were invoked to clarify the impact of the major parameters, such as the modulus and coefficient of thermal expansion of underfill materials, the pitch and diameter of TSV, etc. Upon the analysis results, the design of minimized stress in TSV for the IC integration with TSV interposer was achieved.

Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Dispositifs à structure composée, Compound structure devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Analyse contrainte, Stress analysis, Análisis tensión, Atterrissage, Landing, Aterrizaje, Conception circuit, Circuit design, Diseño circuito, Consommation énergie, Energy consumption, Consumo energía, Contrainte thermomécanique, Thermomechanical stress, Tensión termomecánica, Facteur forme, Form factor, Factor forma, Facteur puissance, Power factor, Factor potencia, Fiabilité, Reliability, Fiabilidad, Fuite, Leak, Salida, Modélisation, Modeling, Modelización, Méthode superposition, Superposition method, Método superposición, Méthode élément fini, Finite element method, Método elemento finito, Méthodologie, Methodology, Metodología, Optimisation, Optimization, Optimización, Structure 3 dimensions, Three dimensional structure, Estructura 3 dimensiones, Trou interconnexion, Via hole, and Agujero interconexión

Three-dimensional integrated circuit (3D IC) with through-silicon-via (TSV) is believed to offer new levels of efficiency, power, performance, and form-factor advantages over the conventional 2D IC. However, 3D IC involves disruptive manufacturing technologies compared to conventional 2D IC. TSVs cause significant thermomechanical stress that may seriously affect performance, leakage, and reliability of circuits. In this paper, we discuss an efficient and accurate full-chip thermomechanical stress and reliability analysis tool as well as a design optimization methodology to alleviate mechanical reliability issues in 3D ICs. First, we analyze detailed thermomechanical stress induced by TSVs in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis (FEA) simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Domaines interdisciplinaires: science des materiaux; rheologie, Cross-disciplinary physics: materials science; rheology, Science des matériaux, Materials science, Méthodes de dépôt de films et de revêtements; croissance de films et épitaxie, Methods of deposition of films and coatings; film growth and epitaxy, Electrodépôt, Electrodeposition, electroplating, Chimie, Chemistry, Chimie analytique, Analytical chemistry, Méthodes électrochimiques, Electrochemical methods, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Acide méthanesulfonique, Methanesulfonic acid, Acido metano sulfónico, Additif, Additives, Cavité dans réseau, Voids, Champ électrique, Electric fields, Circuit intégré, Integrated circuits, Cuivre, Copper, Distribution champ, Field distribution, Distribución campo, Dépôt électrolytique, Electrodeposition, Effet champ électrique, Electric field effects, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Interconnexion, Interconnections, Logiciel, Computer software, Placage, Plating, Propriété électrochimique, Electrochemical properties, Propiedad electroquímica, Trou interconnexion, Via hole, Agujero interconexión, Voltammétrie cyclique, Cyclic voltammetry, Voltametría cíclica, 8245R, 8540H, Electroplating, Simulation, and Through-silicon-via

The filling mechanism of a special through silicon vias (TSV) structure is investigated by electrochemical test and simulation technique compared with the conventional TSV structure in this paper. The effects of additives in methanesulfonic solution are briefly studied by cyclic voltammetry to obtain the suitable copper plating condition for conventional TSV. The electric field distribution in the special TSV during the electrodeposition has been simulated by the software ANSYS. Different from the conventional TSV, the electric field gathered at the bottom of the via in the initial stage of special TSV, which benefit the bottom up filling in the via. And after the deposited copper spread to the whole surface of the chip, the electric field distribution becomes similar to the conventional TSV. With the help of the additives, the void free copper electrodeposition in special TSV was finally achieved.

Electronics, Electronique, Optics, Optique, Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Tubes électroniques, masers, Electronic tubes, masers, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits hyperfréquences, circuits intégrés hyperfréquences, lignes de transmission hyperfréquences, circuits à ondes submillimétriques, Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits, Champ magnétique, Magnetic field, Campo magnético, Champ électrique, Electric field, Campo eléctrico, Circuit intégré, Integrated circuit, Circuito integrado, Couche double, Double layers, Electromagnétisme, Electromagnetism, Electromagnetismo, Fréquence coupure, Cut off frequency, Frecuencia corte, Guide onde, Waveguide, Guía onda, Interconnexion, Interconnection, Interconexión, Ligne microbande, Microstrip line, Línea microbanda, Ligne transmission, Transmission line, Línea transmisión, Perte de retour, Return loss, Pérdida de retorno, Revêtement multicouche, Multilayer coating, Revestimiento multicapa, Simulation, Simulación, Structure onde lente, Slow wave structure, Estructura onda lenta, Trou interconnexion, Via hole, Agujero interconexión, Tube onde progressive, Travelling wave tube, Tubo onda progresiva, Vitesse phase, Phase velocity, Velocidad fase, Intégration sur substrat, Substrate integration, Slow-wave effect, substrate integrated waveguide (SIW), and transition from microstrip to slow-wave SIW (SW-SIW)

This paper describes a new concept of substrate integrated waveguide (SIW): a slow-wave substrate integrated waveguide (SW-SIW). Compared to a conventional SIW, the proposed topology requires a double-layer substrate with a bottom layer including internal metallized via-holes connected to the bottom conductive plane. The slow-wave effect is obtained by the physical separation of electric and magnetic fields in the structure. Electromagnetic simulations show that this topology of SIW allows decreasing the longitudinal dimension by more than 40% since the phase velocity is significantly smaller than that of a classical SIW. Simultaneously, the lateral dimension of the waveguide is also reduced. By considering a double-layer technology, SW-SIWs exhibiting a cutoff frequency of 9.3 GHz were designed, fabricated, and measured. The transversal dimension and the phase velocity of the proposed SW-SIW are both reduced by 40% as compared to a classical SIW designed for the same cutoff frequency, leading to a significant surface reduction. Moreover, an original kind of taper is proposed to achieve a good return loss when the SW-SIW is fed by a microstrip transmission line.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Carte électronique, Printed circuit board, Tarjeta electronica, Charge thermique, Thermal load, Carga térmica, Circuit imprimé, Printed circuit, Circuito imprimido, Circuit intégré, Integrated circuit, Circuito integrado, Concentration contrainte, Stress concentration, Concentración restringida, Configuration géométrique, Geometrical configuration, Configuración geométrica, Contrainte thermique, Thermal stress, Tensión térmica, Cuivre, Copper, Cobre, Cycle thermique, Thermal cycle, Ciclo térmico, Densité élevée, High density, Densidad elevada, Dilatation thermique, Thermal expansion, Dilatación térmica, Dissipateur thermique, Heat sink, Disipador térmico, Durabilité, Durability, Durabilidad, Défaillance, Failures, Fallo, Déformation, Deformation, Deformación, Désadaptation, Mismatching, Desadaptación, Essai environnement, Environmental test, Prueba ambiental, Fatigue thermique, Thermal fatigue, Fatiga térmica, Fiabilité, Reliability, Fiabilidad, Gestion température packaging électronique, Thermal management (packaging), Interconnexion, Interconnection, Interconexión, Matière plastique, Plastics, Material plástico, Méthode numérique, Numerical method, Método numérico, Méthode élément fini, Finite element method, Método elemento finito, Rupture, Ruptura, Structure flexible, Flexible structure, Estructura flexible, Système refroidissement, Cooling system, Sistema enfriamiento, Trou interconnexion, Via hole, and Agujero interconexión

The thermal fatigue of vias in rigid―flex printed circuit boards (PCB) is considered in the paper. Dedicated printed circuit boards have been designed with different geometrical configurations (plating thickness, drilled hole diameter and PCB thickness). The PCB is made of hundreds of vias or holes which are wired by copper path to create a daisy chain. The PCB is subject to cyclic thermal loading (-55 °C, + 125 °C). Electrical connectivity is recorded during tests. Cross sectioning is performed finally to characterize the loss of electrical connectivity. Fracture of plated copper, due to the thermal expansion mismatch between constituents, is shown to be responsible for the failure of the PCB. In addition to environmental tests, finite element model is developed to analyze the deformation of PCBs during thermal cycling. Areas of strain concentration determined by Finite Element Analysis (FEA) are consistent with locations where cracks were observed in experiments. In addition, the numerical estimation of the plastic strain increment per cycle enables the prediction of the fatigue life. The results confirm that for rigid flex boards, the fatigue life of vias increases with higher plating thickness, larger drilled hole size and lower PCB thickness. Numerical results are shown to be in good agreement with experiments.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Assistance ordinateur, Computer aid, Asistencia ordenador, Circuit imprimé, Printed circuit, Circuito imprimido, Circuit intégré, Integrated circuit, Circuito integrado, Déformation, Deformation, Deformación, Encapsulation, Encapsulación, Interconnexion, Interconnection, Interconexión, Logiciel, Software, Logicial, Modélisation, Modeling, Modelización, Packaging électronique, Electronic packaging, Packaging electrónico, Silicium, Silicon, Silicio, Simulation ordinateur, Computer simulation, Simulación computadora, Trou interconnexion, Via hole, Agujero interconexión, Visualisation, Visualization, Visualización, Vobulation fil, and Wire sweep

The rapid development of computing software has facilitated multifarious research in integrated circuit (IC) packaging. Complicated and complex processes can be visualized via simulation modeling with this software. The applications of aided software enhance the fundamental physicochemical understanding and visualization of the IC encapsulation process. In this article, fluid-structure interaction (FSI) during IC encapsulation through computer-aided simulation is reviewed based on the amount of substantial work conducted from the past decades to the present. FSI phenomena in various IC encapsulations, such as wire sweep, paddle shift, lead frame deformation, IC chip, and through-silicon via (TSV) deformation, is considered in the review. The significance and challenges of FSI analysis are also highlighted in this article.

Electronics, Electronique, Condensed state physics, Physique de l'état condensé, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs optoélectroniques, Optoelectronic devices, Dispositif optoélectronique, Optoelectronic device, Dispositivo optoelectrónico, Cathode, Cátodo, Circuit intégré, Integrated circuit, Circuito integrado, Contact direct, Direct contact, Contacto directo, Contamination, Contaminación, Courant fuite, Leakage current, Corriente escape, Court circuit, Short circuit, Cortocircuito, Diode électroluminescente organique, Organic light emitting diodes, Durabilité, Durability, Durabilidad, Durée vie, Lifetime, Tiempo vida, Défaillance, Failures, Fallo, Défaut, Defect, Defecto, Electronique organique, Organic electronics, Electrónica orgánica, Fiabilité, Reliability, Fiabilidad, Interconnexion, Interconnection, Interconexión, Mélange polymère, Polymer blends, Méthode en solution, Growth from solution, Método en solución, Piqûre corrosion, Pinhole, Picadura corrosión, Prévention, Prevention, Prevención, Simulation HIL, Hardware in the loop simulation, Simulación HIL, Sodium, Sodio, Styrènesulfonate polymère, Styrenesulfonate polymer, Estireno sulfonato polímero, Thiophène dérivé polymère, Thiophene derivative polymer, Tiofeno derivado polímero, Traitement matériau, Material processing, Tratamiento material, Trou interconnexion, Via hole, Agujero interconexión, 8560J, Couche d'injection de trous, Hole injection layer, Leakage-current, PEDOT:PSS, Repair, and Sodium-hypochlorite

Pinholes in the emitting layer of an organic light emitting diode (OLED), e.g. induced by particle contamination or processing flaws, lead to direct contact between the hole-injection layer (HIL) and the cathode. The resulting short circuits give rise to catastrophic device failure. We demonstrate that these short circuits can be effectively prevented by an oxidative treatment of the HIL with aqueous sodium hypochlorite (NaClO(aq), bleach), which locally lowers the conductivity of the HIL (i.e. poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)) by more than eight orders of magnitude while leaving the emitting layer virtually unaffected. The oxidizer treatment is evidenced by an order of magnitude reduction in leakage current and strong reduction in the number of bright spots in the emitting area, without affecting the device lifetime. Diode behavior is even recovered in deliberately flawed devices containing 80 μm sized defects.

Electronics, Electronique, Computer science, Informatique, Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Electronique de puissance, alimentations électriques, Power electronics, power supplies, Alimentation électrique, Power supply, Alimentación eléctrica, Circuit intégré, Integrated circuit, Circuito integrado, Conception assistée, Computer aided design, Concepción asistida, Conception circuit, Circuit design, Diseño circuito, Consommation électricité, Electric power consumption, Consumo electricidad, Densité intégration, Integration density, Densidad integración, Electronique faible puissance, Low-power electronics, Electronique puissance, Power electronics, Electrónica potencia, Empilement, Stacking, Apilamiento, Grande puissance, High power, Gran potencia, Implantation circuit intégré, Integrated circuit layout, Interconnexion, Interconnection, Interconexión, Modèle 3 dimensions, Three dimensional model, Modelo 3 dimensiones, Réseau électrique, Electrical network, Red eléctrica, Silicium, Silicon, Silicio, Structure 3 dimensions, Three dimensional structure, Estructura 3 dimensiones, Technologie planaire, Planar technology, Tecnología planar, Trou interconnexion, Via hole, and Agujero interconexión

Three-dimensional (3D) integrated circuits, which use a vertically stacked design of 2D planar chips in a 3D arrangement using through-silicon-via (TSV) technology have been developed to minimise chip footprint, enable higher integration density, decrease power consumption and reduce fabrication cost. Floorplanning without considering power can increase the number of power TSVs and bumps needed to solve IR drop constraint in 3D power delivery network. In this study, the authors propose a methodology for minimising the power TSVs and bumps based on power-aware floorplanning using specific power patterns to solve IR drop constraint on the 3D power delivery network. The authors' methodology moves high power-consuming blocks to the dedicated pattern area which is able to minimise the number of power TSVs and bumps while solving the IR drop constraint. The simulation results show that the proposed method can reduce the total number of power TSVs and bumps by 13.7 and 12.2%, respectively, after power-aware floorplanning while solving the IR drop constraint.

Electrical engineering, Electrotechnique, Physics, Physique, Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Domaines classiques de la physique (y compris les applications), Fundamental areas of phenomenology (including applications), Optique, Optics, Eléments, dispositifs, et systèmes optiques, Optical elements, devices, and systems, Ordinateurs optiques, éléments logiques, dispositifs d'interconnexion, commutateurs; réseaux neuronaux, Optical computers, logic elements, interconnects, switches; neural networks, Sciences appliquees, Applied sciences, Electronique, Electronics, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Divers, Miscellaneous, Circuits optiques et optoélectroniques, Optical and optoelectronic circuits, Optique intégrée. Fibres et guides d'onde optiques, Integrated optics. Optical fibers and wave guides, Telecommunications et theorie de l'information, Telecommunications and information theory, Télécommunications, Telecommunications, Systèmes, réseaux et services de télécommunications, Systems, networks and services of telecommunications, Transmission et modulation (techniques et équipements), Transmission and modulation (techniques and equipments), Accès multiple, Multiple access, Acceso múltiple, Circuit RC, RC circuit, Circuito RC, Circuit VLSI, VLSI circuit, Circuito VLSI, Circuit intégré puissance, Power integrated circuits, Circuit intégré, Integrated circuit, Circuito integrado, Comportement parasite, Parasitic behavior, Conducta parásito, Consommation électricité, Electric power consumption, Consumo electricidad, Electromagnétisme, Electromagnetism, Electromagnetismo, Interconnexion, Interconnection, Interconexión, Mode TEM, TEM mode, Modo Onda Electromagnética Transversal, Mode transversal, Transverse mode, Modo transversal, Méthode analytique, Analytical method, Método analítico, Passivité, Passivity, Pasividad, Simulateur, Simulator, Simulador, Simulation système, System simulation, Simulación sistema, Structure onde lente, Slow wave structure, Estructura onda lenta, Substrat semiconducteur, Semiconductor substrate, Substrato semiconductor, Théorie quasi statique, Quasi static theory, Teoría cuasiestática, Trou interconnexion, Via hole, Agujero interconexión, Tube onde progressive, Travelling wave tube, Tubo onda progresiva, 4279T, 4282D, 6125M, 6143D, 6182B, 6630F, 8540L, Macromodélisation, Macromodeling, RC model, passivity, and through silicon vias (TSVs)

Parasitic RC behavior of VLSI interconnects has been the major bottleneck in terms of latency and power consumption of ICs. Recent 3-D ICs promise to reduce the parasitic RC effect by making use of through silicon vias (TSVs). It is therefore essential to extract the RC model of TSVs to assess their promise. Unlike interconnects on metal layers, TSVs exhibit slow-wave and dielectric quasi-transverse-electromagnetic modes due to the coupling to the semiconducting substrate. This TSV behavior can be simulated using analytical methods, 2-D/3-D quasi-static simulators, or 3-D full-wave electromagnetic simulators. This paper describes a methodology to extract parasitic RC models from such simulation data for interconnects in a 3-D IC.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Etat condense: structure, proprietes mecaniques et thermiques, Condensed matter: structure, mechanical and thermal properties, Propriétés de transport (non électroniques), Transport properties of condensed matter (nonelectronic), Diffusion dans les solides, Diffusion in solids, Diffusion dans les nanomatériaux et nanostructures, Diffusion in nanoscale solids, Surfaces et interfaces; couches minces et trichites (structure et propriétés non électroniques), Surfaces and interfaces; thin films and whiskers (structure and nonelectronic properties), Surfaces solides et interfaces solide-solide, Solid surfaces and solid-solid interfaces, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Additif, Additive, Aditivo, Adsorption, Adsorción, Ajustement courbe, Curve fitting, Ajustamiento curva, Circuit intégré, Integrated circuit, Circuito integrado, Condition aux limites, Boundary condition, Condiciones límites, Cuivre, Copper, Cobre, Densité courant, Current density, Densidad corriente, Diffusion(transport), Diffusion, Electrolyte, Electrólito, Interconnexion, Interconnection, Interconexión, Interface, Interfase, Lanthane Manganite, Lanthanum Manganites, Lantano Manganito, Optimisation, Optimization, Optimización, Paramètre cinétique, Kinetic parameter, Parámetro cinético, Prévision, Forecasting, Previsión, Simulation numérique, Numerical simulation, Simulación numérica, Strontium Manganite, Strontium Manganites, Estroncio Manganito, Structure 3 dimensions, Three dimensional structure, Estructura 3 dimensiones, Trou interconnexion, Via hole, Agujero interconexión, Vérification, Verification, Verificación, 6630P, Copper electro-chemical deposition, Superfilling, Tafel curve, and Through silicon via

Copper electro-chemical deposition (ECD) of through silicon via (TSV) is a key challenge of 3D integration. This paper presents a numerical modeling of TSV filling concerning the influence of the accelerator and the suppressor. The diffusion-adsorption model was used in the simulation and effects of the additives were incorporated in the model. The boundary conditions were derived from a set of experimental Tafel curves with different concentrations of additives, which provided a quick and accurate way for copper ECD process prediction without complicated surface kinetic parameters fitting. The level set method (LSM) was employed to track the copper and electrolyte interface. The simulation results were in good agreement with the experiments. For a given feature size, the current density for superfilling could be predicted, which provided a guideline for ECD process optimization.

Crystallography, Cristallographie cristallogenèse, Chemical industry parachemical industry, Industrie chimique et parachimique, Metallurgy, welding, Métallurgie, soudage, Condensed state physics, Physique de l'état condensé, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Etat condense: structure, proprietes mecaniques et thermiques, Condensed matter: structure, mechanical and thermal properties, Structure des liquides et des solides; cristallographie, Structure of solids and liquids; crystallography, Structure de solides cristallins particuliers, Structure of specific crystalline solids, Domaines interdisciplinaires: science des materiaux; rheologie, Cross-disciplinary physics: materials science; rheology, Science des matériaux, Materials science, Diagrammes de phases et microstructures développées par solidification et par transformations de phases solide-solide, Phase diagrams and microstructures developed by solidification and solid-solid phase transformations, Transformations de phases solide-solide à composition constante: polymorphes, massives, ordre-désordre, Constant-composition solid-solid phase transformations: polymorphic, massive, and order-disorder, Sciences appliquees, Applied sciences, Metaux. Metallurgie, Metals. Metallurgy, Propriétés mécaniques. Rhéologie. Mécanique de la rupture. Tribologie, Mechanical properties and methods of testing. Rheology. Fracture mechanics. Tribology, Fatigue, Autres propriétés mécaniques, Other mechanical properties, Amortissement, Damping, Amortiguación, Carbone, Carbon, Carbono, Kohlenstoff, Effet contrainte, Stress effects, Essai fatigue, Fatigue test, Ensayo fatiga, Dauerschwingversuch, Fatigue, Fatiga, Ermuedung, Fibre carbone, Carbon fiber, Fibra carbón, Kohlefaser, Frottement interne, Internal friction, Frotamiento interno, Innere Reibung, Infiltration chimique phase vapeur, Chemical vapor infiltration, Infiltración química fase vapor, Interface fibre matrice, Matrix fiber interface, Interfase fibra matriz, Limite fatigue, Fatigue limit, Límite fatiga, Ermuedungsgrenze, Matériau composite, Composite material, Material compuesto, Verbundwerkstoff, Métrique, Metric, Métrico, Régime permanent, Steady state, Régimen permanente, Structure cristalline, Crystalline structure, Estructura cristalina, Kristallstruktur, Structure interne, Internal structure, Estructura interna, Transformation phase cristalline, Crystal-phase transformations, Transformation phase, Phase transformation, Transformación fase, Phasenumwandlung, Trou interconnexion, Via hole, Agujero interconexión, 8130H, and Unidirectional C/C composite

Internal friction behavior was utilized as an indirect metric to study structural change in carbon/carbon composites after fatigue tests. In this work, two kinds of unidirectional carbon/carbon composites with different densities were prepared by isothermal chemical vapor infiltration (ICVI), and loaded under stress level of their fatigue limit. The internal friction behavior of the composites after different fatigue cycles was studied. After the initial 104 fatigue cycles, since the matrix began to break and shed, frictional damping that happened between the fiber and matrix interfaces increased and the bulk internal friction increased rapidly. Between 104 and 5 × 105 fatigue cycles, holes formed at interfaces because of continued shedding of the matrix. Since the holes reduced contact area between different phases, frictional damping decreased, as along with the internal friction increment ratio. Between 5 × 105 and 106 fatigue cycles, interfacial bonding between carbon fiber and matrix was in a steady state, so structure and internal friction of the composites did not change. The results revealed that internal friction was an effective method to characterize structural change of carbon/carbon composites after fatigue tests.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Generalites, General, Instruments, appareillage, composants et techniques communs à plusieurs branches de la physique et de l'astronomie, Instruments, apparatus, components and techniques common to several branches of physics and astronomy, Microscopes à champ proche, composants et techniques, Scanning probe microscopes, components and techniques, Sciences appliquees, Applied sciences, Electronique, Electronics, Essais, mesure, bruit et fiabilité, Testing, measurement, noise and reliability, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Metaux. Metallurgie, Metals. Metallurgy, Contrôle, Analysing. Testing. Standards, Contrôle non destructif, Nondestructive testing, Circuit intégré, Integrated circuit, Circuito integrado, Integrierte Schaltung, Densité élevée, High density, Densidad elevada, Essai non destructif, Non destructive test, Ensayo no destructivo, Zerstoerungsfreie Pruefung, Gravure, Engraving, Grabado, Interconnexion, Interconnection, Interconexión, Interférence, Interference, Interferencia, Mesure épaisseur, Thickness measurement, Medición espesor, Dickenmessung, Monitorage, Monitoring, Monitoreo, Méthode mesure, Measurement method, Método medida, Métrologie, Metrology, Metrología, Metrologie, Paramètre géométrique, Geometrical parameter, Parámetro geométrico, Phénomène critique, Critical phenomenon, Fenómeno crítico, Rapport aspect, Aspect ratio, Relación dimensional, Rayonnement UV, Ultraviolet radiation, Radiación ultravioleta, Ultraviolettstrahlen, Réflectance spectrale, Spectral reflectance, Réflectomètre, Reflectometer, Reflectómetro, Reflektometer, Réflectométrie, Reflectometry, Reflectometría, Réflexion onde, Wave reflection, Reflexión onda, Réseau (arrangement), Array, Red, Structure 3 dimensions, Three dimensional structure, Estructura 3 dimensiones, Système mesure, Measuring system, Sistema medida, Taille critique, Critical size, Trou interconnexion, Via hole, Agujero interconexión, Etch depth, Rigorous coupled wave analysis (RCWA), Spectroscopic reflectometry, and Through silicon via (TSV)

Through-silicon via (TSV) technology is a key feature for 3D circuit integration. The nondestructive metrology of deep-etched structures with aspect ratio of >10 and patterns with lateral dimensions in the range up to 5 μm remains an challenge and can be overcome by destructive control. In this paper the inspection of TSV depth and critical dimensions (CD) of their opening were performed nondestructively by an industrial thickness measurement tool (UV―VIS spectral reflectometer). The possibilities and limits of in-line optical tools for the characterization of the high density TSV array of high aspect-ratio square vias with tapered profile in Si were examined. TSV with CD from 3 up to 7 μm, pitch in the range of 7―11 μm, and etch depth of 50―70 μm were investigated. The TSV depth was determined using the interference effect between reflected waves from the top and bottom surfaces of the TSV structures. The rigorous coupled wave analysis (RCWA) is successfully applied to the analysis of the spectral reflectance for the determination of the TSV top and bottom CD and profile evaluation. It was shown that this method can be used for the monitoring of geometrical parameters of TSVs with dimensions from 3 μm and aspect ratios up to 17:1. The non-destructive measurement data provide excellent correlation with SEM results.

Electronics, Electronique, Condensed state physics, Physique de l'état condensé, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Etat condense: structure electronique, proprietes electriques, magnetiques et optiques, Condensed matter: electronic structure, electrical, magnetic, and optical properties, Structure électronique et propriétés électriques des surfaces, interfaces, couches minces et structures de basse dimensionnalité, Electronic structure and electrical properties of surfaces, interfaces, thin films and low-dimensional structures, Doubles couches superficielles, barrières de schottky et travail de sortie, Surface double layers, schottky barriers, and work functions, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Matériaux, Materials, Metaux. Metallurgie, Metals. Metallurgy, Transformation de matériaux métalliques, Production techniques, Traitements de surface, Surface treatment, Basse tension, Low voltage, Baja tensión, Niederspannung, Canal n, n channel, Capacité électrique, Capacitance, Capacitancia, Caractéristique électrique, Electrical characteristic, Característica eléctrica, Elektrische Groesse, Circuit intégré, Integrated circuit, Circuito integrado, Integrierte Schaltung, Couche mince, Thin film, Capa fina, Duennschicht, Cuivre, Copper, Cobre, Kupfer, Densité élevée, High density, Densidad elevada, Diminution coût, Cost lowering, Reducción costes, Kostensenkung, Drain, Dren, Dégradation, Degradation, Degradación, Dépôt centrifugation, Spin-on coating, Electronique organique, Organic electronics, Electrónica orgánica, Fullerènes, Fullerenes, Haute performance, High performance, Alto rendimiento, Haute tension, High voltage, Alta tensión, Hochspannung, Injection électron, Electron injection, Inyección electrón, Interconnexion, Interconnection, Interconexión, Interface, Interfase, Grenzflaeche, Matériau électrode, Electrode material, Material electrodo, Mobilité électron, Electron mobility, Movilidad electrón, Elektronenbeweglichkeit, Propriété surface, Surface properties, Propiedad superficie, Oberflaecheneigenschaft, Revêtement centrifugation, Spin-on coatings, Stabilité thermique, Thermal stability, Estabilidad térmica, Thermische Stabilitaet, Traitement surface, Surface treatment, Tratamiento superficie, Oberflaechenbehandlung, Transistor couche mince, Thin film transistor, Transistor capa delgada, Travail sortie, Work function, Función de trabajo, Austrittsarbeit, Trou interconnexion, Via hole, Agujero interconexión, 8105T, 8530T, C60, High-performance, and Surface modification

Exploring suitable electrode materials with sufficiently low work function, ambient stability and low-cost is of great technological importance to the development of n-channel OTFTs. Here, we show that the work function of Cu can be effectively reduced from 4.65 eV to 4.28 eV through surface modification via simply spin-coating a thin layer of branched polyethylenimine (PEI). By exploiting a high-capacitance density gate dielectric (200 nF/cm2), low-voltage (3 V) C60 TFTs with electron mobility (μe) of 3.2 cm2/V s are demonstrated with PEI modified Cu as source-drain (S/D) electrodes. In contrast, the device with Cu S/D electrodes possesses μe of only 1.0 cm2/V s. The improvement in electrical performance of the PEI modified device is attributed to the efficient electron injection at the Cu/C60 interface which resulted from the reduction in work function of Cu. Moreover, upon PEI modification, the bias stability of the device can be obviously enhanced as compared to the unmodified one, and the resultant device exhibits an excellent thermal stability up to 200 °C without appreciable degradation in mobility. The facile modification of low-cost Cu as S/D electrodes for high-performance n-channel OTFTs as well as the low-voltage operation will pave the way for large scale manufacturing of organic electronics.

Electronics, Electronique, Condensed state physics, Physique de l'état condensé, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Domaines interdisciplinaires: science des materiaux; rheologie, Cross-disciplinary physics: materials science; rheology, Science des matériaux, Materials science, Méthodes de dépôt de films et de revêtements; croissance de films et épitaxie, Methods of deposition of films and coatings; film growth and epitaxy, Electrodépôt, Electrodeposition, electroplating, Traitements de surface, Surface treatments, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Capteur mesure, Measurement sensor, Captador medida, Circuit intégré, Integrated circuits, Conductivité électrique, Electrical conductivity, Dioxyde de carbone, Carbon dioxide, Carbono dióxido, Dépôt électrolytique, Electrodeposition, Echauffement destructif, Burnout, Empilement, Stacks, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Formation motif, Patterning, Gravure ionique réactive, Reactive ion etching, Grabado iónico reactivo, Hélium, Helium, Interconnexion, Interconnections, Miniaturisation, Miniaturization, Module multipuce, Multichip modules, Nickel, Packaging électronique, Electronic packaging, Packaging electrónico, Pastille électronique, Wafers, Plasma couplé inductivement, Inductively coupled plasma, Résistance électrique, Resistors, Résistivité électrique, Electric resistivity, Signal électrique, Electrical signal, Señal eléctrica, Silicium, Silicon, Solvant supercritique, Supercritical solvent, Disolvente supercrítico, Structure 3 dimensions, Three dimensional structure, Estructura 3 dimensiones, Technologie planaire, Planar technology, Tecnología planar, Traitement thermique, Heat treatments, Trou interconnexion, Via hole, Agujero interconexión, 0707D, 8116R, 8540H, 3D integration, Emulsion, Nickel electroplating, Packaging, Supercritical-CO2, and TSV

Compared to the 2D plane, 3D integrated circuit (IC) structure could provide larger patterning areas by stacking the multi-planar chips, in which the electrical signals can be vertically conducted via through-silicon vias (TSVs). Thus, its advantages are lowered costs and reduced packaging space, size and weight. In this study, the TSVs used for 3D integration are fabricated and characterized. Four through holes with a diameter of 70 μm on a silicon wafer are first etched by inductively coupled plasma reactive ion etch (ICP) and filled by nickel electroplating in supercritical CO2 emulsion. The chip is cut for observation and examination of the cross-sectional view of the TSVs. For hermeticity testing, a helium leaking detector was performed on all TSVs before and after the heat treatment process (heating up to 350 C). The average electrical resistance across the TSVs was measured to be 0.01 Ω. Then the fabricated TSVs can be applied a maximum current of 10 A continuously without burnout.

Electronics, Electronique, Mechanics acoustics, Mécanique et acoustique, Physics, Physique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Etat condense: structure, proprietes mecaniques et thermiques, Condensed matter: structure, mechanical and thermal properties, Surfaces et interfaces; couches minces et trichites (structure et propriétés non électroniques), Surfaces and interfaces; thin films and whiskers (structure and nonelectronic properties), Surfaces fluides et interfaces fluide-fluide, Fluid surfaces and fluid-fluid interfaces, Energie de surface (tension superficielle, tension interfaciale, angle de contact, etc.), Surface energy (surface tension, interface tension, angle of contact, etc.), Surfaces solides et interfaces solide-solide, Solid surfaces and solid-solid interfaces, Propriétés mécaniques et acoustiques; adhérence, Mechanical and acoustical properties; adhesion, Interfaces solide-fluide, Solid-fluid interfaces, Cinétique d'adsorption et de désorption; évaporation et condensation, Adsorption and desorption kinetics; evaporation and condensation, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Dispositifs à structure composée, Compound structure devices, Actionneur électrostatique, Electrostatic actuators, Angle contact, Contact angle, Autoalignement, Self alignment, Autoalineación, Composé hydrophile, Hydrophilic compound, Compuesto hidrofilo, Contact glissant, Sliding contact, Contacto deslizante, Contact mécanique, Mechanical contacts, Dispositif microélectromécanique, Microelectromechanical device, Dispositivo microelectromecánico, Dispositif électrostatique, Electrostatic devices, Etude expérimentale, Experimental study, Fiabilité, Reliability, Force électrostatique, Electrostatic force, Fuerza electrostática, Frottement sec, Dry friction, Frotamiento seco, Frottement statique, Stiction, Gouttelette, Droplets, Hydrophobicité, Hydrophobicity, Hidrofobicidad, Hystérésis, Hysteresis, Liquide ionique, Ionic liquid, Líquido iónico, Palier, Bearings, Rainure, Groove, Ranura, Résistance contact, Contact resistance, Tension superficielle, Surface tension, Transducteur capacitif, Capacitive transducer, Transductor capacitivo, Trou interconnexion, Via hole, Agujero interconexión, Electrostatic actuation, Liquid bearing, ionic liquid, liquid ring bearing, rotary stage, superhydrophobic, and through-silicon-vias (TSVs)

We present an electrostatically actuated rotary stage featuring liquid rings, which serve as both mechanical bearings and electric connections between the rotor and the substrate. The liquid rings are formed by confining a liquid inside hydrophilic grooves and repelling it from the superhydrophobic surfaces outside the grooves. Made of a fluid, the liquid-ring bearing avoids the dry friction of the solid bearings, significantly improving the reliability. Formed as rings, it avoids the resistance of contact-angle hysteresis sliding over droplets, and hence dramatically reducing the static friction. Furthermore, surface tension facilitates the self-alignment of the rotor to the substrate and stator during the assembly and provides the stability against drift and shock during operation. Electrically, each liquid ring passes an independent electric signal, allowing a direct electrical path between the substrate and potential components on the rotor. A three-phase electrostatic rotary stage has been design, fabricated, and tested. The minimum torque to initiate the rotation is ~2.5nN · m - hundreds of times smaller than droplet-based counterparts. The device has operated successfully by applying sequential voltages of 50 VDC between the rotor and the stators. The electric transmission has been verified by powering an LED on a rotating rotor. This is the first report of an electrostatically actuated rotating microdevice with a liquid bearing and a direct power transmission.

Electronics, Electronique, Condensed state physics, Physique de l'état condensé, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Domaines interdisciplinaires: science des materiaux; rheologie, Cross-disciplinary physics: materials science; rheology, Science des matériaux, Materials science, Matériaux particuliers, Specific materials, Autres matériaux, Other materials, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Divers, Miscellaneous, Composé III-VI, III-VI compound, Compuesto III-VI, Adhésif, Adhesive, Adhesivo, Alumine, Alumina, Alúmina, Amine polymère, Amine polymer, Amina polímero, Arylamine, Arilamina, Bicouche, Bilayers, Circuit intégré, Integrated circuit, Circuito integrado, Circuit transistor effet champ, Field effect transistor circuits, Délaminage, Delamination, Delaminación, Dérivé du pentacène, Pentacene derivatives, Pentaceno derivado, Electronique organique, Organic electronics, Electrónica orgánica, Estampage, Die forging, Estampación, Evaluation performance, Performance evaluation, Evaluación prestación, Interconnexion, Interconnection, Interconexión, Molécule petite, Small molecule, Molécula pequeña, Méthode ALE, Atomic layer epitaxial growth, Méthode couche atomique, Atomic layer method, Método capa atómica, Polymère, Polymer, Polímero, Réseau interconnexion, Interconnection network, Red interconexión, Silane organique, Organic silane, Silano orgánico, Siloxane(diméthyl) polymère, Dimethylsiloxane polymer, Siloxano(dimetil) polímero, Transistor effet champ, Field effect transistor, Transistor efecto campo, Trou interconnexion, Via hole, Agujero interconexión, 8105L, 8530T, Al2O3, Bilayer, Circuits, Organic transistors, and Via-hole

We report on a reverse stamping method to produce via-holes in circuits comprising acene-based top-gate organic field-effect transistors (OFETs) having a CYTOP/Al2O3 (by atomic layer deposition) bilayer gate dielectric. This method relies on the weak adhesive force that exists between a small molecule acene film and a polymer to enable easy delamination of the bilayer gate dielectric by using a PDMS stamp. We demonstrate the effectiveness of this method by fabricating simple circuits using top-gate triisopropylsilylethynyl pentacene (TIPS-pentacene)/poly (triarylamine) (PTAA) OFETs.

Crystallography, Cristallographie cristallogenèse, Electronics, Electronique, Metallurgy, welding, Métallurgie, soudage, Condensed state physics, Physique de l'état condensé, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Etat condense: structure, proprietes mecaniques et thermiques, Condensed matter: structure, mechanical and thermal properties, Structure des liquides et des solides; cristallographie, Structure of solids and liquids; crystallography, Etat cristallin (incluant les mouvements moléculaires dans les solides), Crystalline state (including molecular motions in solids), Théorie de la structure cristalline, symétrie cristalline; calculs et modélisation, Theory of crystal structure, crystal symmetry; calculations and modeling, Structure de solides cristallins particuliers, Structure of specific crystalline solids, Sciences appliquees, Applied sciences, Metaux. Metallurgie, Metals. Metallurgy, Propriétés mécaniques. Rhéologie. Mécanique de la rupture. Tribologie, Mechanical properties and methods of testing. Rheology. Fracture mechanics. Tribology, Couche mince, Thin films, Cuivre, Copper, Dépôt centrifugation, Spin-on coating, Effet contrainte, Stress effects, Encapsulation, Epaisseur, Thickness, Essai matériau, Materials testing, Etude théorique, Theoretical study, Fiabilité, Reliability, Flexibilité, Flexibility, Liaison matériau, Bonding, Mode empilement, Stacking sequence, Modo apilamiento, Modèle structure, Structural models, Modélisation, Modelling, Métallisation, Metallizing, Méthode élément fini, Finite element method, Pastille électronique, Wafers, Polymère, Polymers, Propriété mécanique, Mechanical properties, Puce électronique, Chip, Pulga electrónica, Simulation numérique, Digital simulation, Structure cristalline, Crystal structure, Système sur puce, System on a chip, Topologie, Topology, Trou interconnexion, Via hole, Agujero interconexión, 6150A, Substrat silicium, 3D, FEM thermomechanical simulation, back-to-face, chip-to-wafer stacking, and reliability

Chip-to-wafer stacking is a key enabling technology for two and half dimension (2.5D) as well as for three dimension (3D), with technological challenges driven by the increase of the die surface and the number of input/outputs (I/Os) and the reduction of the vertical dimensions. In our investigation, chips were assembled using a back-to-face approach on a silicon interposer containing copper through-silicon vias (TSVs). This technology is based on the realization of a high-topology redistribution layer passing over the dies bonded with the active face up on the interposer by using a polymer layer. This architecture is attractive because of the reduction of the chip thickness to an ultrathin dimension, and can offer substantial advantages in terms of design flexibility and technology cost. In this architecture, chip bonding strategies are compared: several bonding materials were tested either on the die side using die-attach film or on the bottom side of the interposer using wafer-level spin-coated polymers. Then, a novel brick (sequence) of processes consisting of high-topology encapsulation and metallization was fully developed to connect the top dies to the bottom wafer. The resulting structure has been modeled through the temperature cycles seen during fabrication using a thermomechanical finite element modeling (FEM) simulation for different geometries and materials. The results indicate a moderate level of stress in the stacked film layers with some concentration in localized regions of the topology. Electrical tests have also been completed at the wafer level, showing low resistances and high yield at front-side and at the back-side level after TSV exposure. Successful reliability tests have also been carried out and support the good mechanical behavior of this integration.

Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Généralités (incluant les aspects économiques et industriels), General (including economical and industrial fields), Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Algorithme génétique, Genetic algorithm, Algoritmo genético, Assemblage brasage tendre, Soldered joint, Junta soldada, Assemblage circuit intégré, Integrated circuit bonding, Circuit intégré, Integrated circuit, Circuito integrado, Conception optimale, Optimal design, Concepción optimal, Consommation électricité, Electric power consumption, Consumo electricidad, Convergence numérique, Numerical convergence, Convergencia numérica, Cuivre, Copper, Cobre, Cycle thermique, Thermal cycle, Ciclo térmico, Densité élevée, High density, Densidad elevada, Dilatation thermique, Thermal expansion, Dilatación térmica, Durcissement, Hardening, Endurecimiento, Electronique faible puissance, Low-power electronics, Empilement, Stacking, Apilamiento, Etat actuel, State of the art, Estado actual, Evaluation performance, Performance evaluation, Evaluación prestación, Fiabilité, Reliability, Fiabilidad, Industrie électronique, Electronics industry, Industria electrónica, Interconnexion, Interconnection, Interconexión, Matière plastique, Plastics, Material plástico, Modèle 3 dimensions, Three dimensional model, Modelo 3 dimensiones, Méthode élément fini, Finite element method, Método elemento finito, Packaging électronique, Electronic packaging, Packaging electrónico, Phosphure de silicium, Silicon phosphides, Rupture, Ruptura, Silicium, Silicon, Silicio, Trou interconnexion, Via hole, Agujero interconexión, Système en boîtier, and System in package

The state of the art for electronic industries tends to offer products with smaller scales, lower cost, larger storage space, multi-functionality and low-power consumption. The latest package technology has advanced towards three-dimensional (3-D) system in package (SiP) design. However, reliability of interconnects becomes an important issue due to the complicated structure induced stress sensitivity for fractures. Therefore, optimizing the design is essential to improve reliability, especially for the delicate Through-Silicon Via (TSV) which is fabricated using high density interconnect technology. A 3-D TSV stacked-chips package model is constructed by finite element analysis (FEA) to investigate the thermo-mechanical behavior for packages stressed under temperature cycle test (TCT). The global/ local method with convergence analyses are jointly applied and achieved an improvement of 74.4% in simulation efficiency. The viscoplastic solder joints, and the elastoplastic behavior with isotropic hardening for copper interconnects are considered in this FEA model, in which the maximum equivalent plastic strain is found to be located at the most critical copper bump and treated as an indicator for reliability. The significant factors, such as the CTE (coefficient of thermal expansion) of silicon substrate, silicon chip and TSV copper bump, are selected by using the fractional factorial design, copper; the thickness of silicon chip and the radius of TSV The objective function is constructed from the normalized regression model according to the response surface method. The results show that the optimal design performs a significant improvement by up to 43.416% for the reduced equivalent plastic strain after genetic algorithm (GA) optimization. To cope with design for manufacturability (DfM), the interval genetic algorithm (IGA) method is introduced for exploring the optimum interval range based on the defined objective error. Finally, the sensitivity analysis is conducted for each significant factor to determine the priority of accuracy control.