ELECTRONIC industries, INDUSTRIAL design, AUTOMATION, SYSTEMS on a chip, FIELD programmable gate arrays, DIGITAL signal processing, and COMPUTER-aided design
Electronic-system-level (ESL) design tools, verification and power analysis lead the pack at the 42nd Design Automation Conference to be held in Anaheim, California on June 13-17, 2005. Synfora will show the 5.01 release of its PICO Express application-engine synthesis tool for system-on-a-chip design. The new release features enhanced capabilities for algorithms in several application areas. Celoxica will show RC10 programmable platform for ESL training, design evaluation, and rapid prototyping. Fitted with a high-density field programmable gate arrays (FPGA), the board features Virtual Peripherals that enable applications programmed into the FPGA to connect to PC-hosted Ethernet and video resources. Meanwhile, AccelChip’s 2005.1 version of Digital Signal Processing (DSP) Synthesis provides a Matlab/Simulink design flow for DSP implementation in FPGA.
ELECTRONIC apparatus & appliances, ENGINEERING design, ELECTRONICS, ENGINEERING, and AUTOMATION
Evaluates several Electronic Design Automation tools. Important features of Cadence's First Encounter system for virtual prototyping; Effectiveness of System Verilog language in providing support for assertion-based verification. INSETS: ENGINEERS SOUND OFF ONLINE;NEED MORE INFORMATION?.
ELECTRONICS, COMPUTER hardware description languages, INTEGRATED circuits, AUTOMATION, and DESIGN
Reports developments related to electronic design automation. Tools to eliminate off-chip passives and the performance-draining characteristics for designers; Innovations in system-level design languages; Introduction of silicon virtual prototyping.
ENGINEERING design, ELECTRONIC systems, INDUSTRIAL engineering, INDUSTRIAL design, TECHNOLOGICAL progress, ENERGY consumption, SYSTEMS on a chip, AUTOMATION, STANDARDIZATION, and EMBEDDED computer systems
The article presents forecasts for new developments related to the electronic design automation (EDA) industry for 2008 in the context of new methodologies, tools and standards to achieve the low-power design. It mentions that in 2008, role of advanced techniques and tools such as sequential equivalence checking for verification will be increased to enable system-on-a-chip (SoC) designers to achieve power optimization, and use electronic system-level (ESL) methodologies. It states that in 2008, the industry will agree on a single IEEE standard in the design of power formats, there will be a transition from timing-driven to power-driven place-and-route tools to help designers identify their key sources of power consumption, and designers will try to improve the prototyping process.
ELECTRONICS, AUTOMATION, INDUSTRIAL engineering, and NEW product development
Several electronic design automation-related news reports, gathered as of April 12, 2004, are presented. The three-dimensional parasitic extraction technology enters the next generation in the Q3D Extractor v.6 of the Ansoft company. The tool speeds design of critical nets and interconnect components in integrated circuit packages, on personal computer boards, and in the connection path between them. It serves well in applications where on-chip passives like spirals, vias, meanders, and interdigitated capacitors must be designed and optimized up front to achieve timing closure. Two evaluation and prototyping boards are now available with high-performance field-programmable gate arrays and a wide range of options from the Celoxica company.