RESEARCH RESTART
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1. Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis [2009]

  • Thabet, Farhat, Coussy, Philippe, Heller, Dominique, and Martin, Eric
  • Journal of Signal Processing Systems. Sept, 2009, Vol. 56 Issue 2-3, p167, 20 p.

2. High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping [2009]

  • Leroux, Camille, Jego, Christophe, Adde, Patrick, and Jezequel, Michel
  • Journal of Signal Processing Systems. Dec 2009, Vol. 57 Issue 3, p349, 13 p.

3. A Gbps IPSec SSL Security Processor Design and Implementation in an FPGA Prototyping Platform [2010]

  • Wang, Haixin, Bai, Guoqiang, and Chen, Hongyi
  • Journal of Signal Processing Systems. March 2010, Vol. 58 Issue 3, p311, 14 p.

4. Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders [2012]

  • Chao, Min-An, Shih, Xin-Yu, and Wu, An-Yeu, Andy
  • Journal of Signal Processing Systems. August 2012, Vol. 68 Issue 2, p183, 20 p.

5. On the Rapid Prototyping of a Portable Multi Media Acquisition System for Intelligent Meeting Capture [2014]

  • Agrawal, Pranjal, Kushwah, Aseem, Kumar, Lalan, and Hegde, Rajesh M.
  • Journal of Signal Processing Systems. June 2014, Vol. 75 Issue 3, p233, 11 p.

6. Multi-core DSP-based Vector Set Bits Counters/Comparators [2015]

  • Sklyarov, Valery and Skliarova, Iouliia
  • Journal of Signal Processing Systems. Sept, 2015, Vol. 80 Issue 3, p309, 14 p.

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