EMBEDDED computer systems, RAPID prototyping, AUTOMATION, PROGRAMMING languages, and SYSTEMS on a chip
Building distributed deal-time embedded systems requires a stringent methodology, from early requirement capture to full implementation. However, there is a strong link between the requirements and the final implementation (e.g., scheduling and resource dimensioning). Therefore, a rapid prototyping process based on automation of tedious and error-prone tasks (analysis and code generation) is required to speed up the development cycle. In this article, we show how the AADL (Architecture Analysis and Design Language), which appeared in late 2004, helps solve these issues thanks to a dedicated tool suite. We then detail the prototyping process and its current implementation: Ocarina. [ABSTRACT FROM AUTHOR]
ELECTRONIC industries, INDUSTRIAL design, AUTOMATION, SYSTEMS on a chip, FIELD programmable gate arrays, DIGITAL signal processing, and COMPUTER-aided design
Electronic-system-level (ESL) design tools, verification and power analysis lead the pack at the 42nd Design Automation Conference to be held in Anaheim, California on June 13-17, 2005. Synfora will show the 5.01 release of its PICO Express application-engine synthesis tool for system-on-a-chip design. The new release features enhanced capabilities for algorithms in several application areas. Celoxica will show RC10 programmable platform for ESL training, design evaluation, and rapid prototyping. Fitted with a high-density field programmable gate arrays (FPGA), the board features Virtual Peripherals that enable applications programmed into the FPGA to connect to PC-hosted Ethernet and video resources. Meanwhile, AccelChip’s 2005.1 version of Digital Signal Processing (DSP) Synthesis provides a Matlab/Simulink design flow for DSP implementation in FPGA.
ENGINEERING design, ELECTRONIC systems, INDUSTRIAL engineering, INDUSTRIAL design, TECHNOLOGICAL progress, ENERGY consumption, SYSTEMS on a chip, AUTOMATION, STANDARDIZATION, and EMBEDDED computer systems
The article presents forecasts for new developments related to the electronic design automation (EDA) industry for 2008 in the context of new methodologies, tools and standards to achieve the low-power design. It mentions that in 2008, role of advanced techniques and tools such as sequential equivalence checking for verification will be increased to enable system-on-a-chip (SoC) designers to achieve power optimization, and use electronic system-level (ESL) methodologies. It states that in 2008, the industry will agree on a single IEEE standard in the design of power formats, there will be a transition from timing-driven to power-driven place-and-route tools to help designers identify their key sources of power consumption, and designers will try to improve the prototyping process.