System on a chip, Technology development, Technology overview, Semiconductor industry -- Product development, and Semiconductors -- Innovations
ACCORDING TO GARTner Dataquest's Gary Smith, the most common system-on-a-chip (SOC) design flow today includes the silicon virtual IC prototype. The first EDA tools to create a silicon virtual prototype [...]
Electronic News (1991). April 21, 1997, Vol. 43 Issue 2164, p50, 2 p.
Technology development, Programmable logic array, Performance improvement, and Programmable logic devices -- Development and progression
The design verification cycle is a critical part of the design process that must be examined before design reuse or programmable systems-on-a-chip become a normal part of high performance, high capacity programmable logic. The design verification cycle traditionally includes debugging, redesign steps and prototyping. A minimized design verification cycle is one advantage that separates standard-cell ASICs and gate arrays from programmable logic. The indeterminate nature of the programmable logic debugging process hinders compression. The two most commonly used approaches for finding design defects are the JTAG and SCAN methodologies. Design re-layout is another methodology, which is normally used for SRAM-based FPGA design.
Electronic News (1991). July 22, 2002, Vol. 48 Issue 30, p12, 1 p.
Application-specific integrated circuit, Technology development, Application-specific integrated circuits -- Research, and Semiconductor industry -- Research
ASICs are expensive and getting evermore so. Mask sets for some sub-0.13-micron processes are breaking the $1 million mark, which for most designers makes small-volume production or even prototyping prohibitively [...]