Electronic News (1991). April 21, 1997, Vol. 43 Issue 2164, p56, 2 p.
Technology overview, Technology application, Application-Specific Integrated Circuit, Integrated circuit design, and Application-specific integrated circuits -- Design and construction
ASIC designers are moving to high density FPGAs or complex programmable logic devices (CPLD) to shorten development times, but these devices are intended for use as extensions of programmable logic devices (PLD), not ASICs. ASIC designers are unfamiliar with the chip and system design issues, or the security concerns related to FPGAs and CPLDs. Flash-based FPGAs provide ASIC designers with reprogrammable ASIC solutions for rapid prototyping and design verification. These devices are based on a standard ASIC design environment and provide cost/performance benefits comparable to those of SRAM-based FPGAs. They work seamlessly with ASIC design environments.
Electronic News (1991). July 22, 2002, Vol. 48 Issue 30, p12, 1 p.
Application-specific integrated circuit, Technology development, Application-specific integrated circuits -- Research, and Semiconductor industry -- Research
ASICs are expensive and getting evermore so. Mask sets for some sub-0.13-micron processes are breaking the $1 million mark, which for most designers makes small-volume production or even prototyping prohibitively [...]
Electronic News (1991). April 28, 1997, Vol. 43 Issue 2165, p16, 1 p. photograph
Application-Specific Integrated Circuit, Hardware product development, VLSI Technology Inc. -- Product development -- 00309176, VLSI Technology VSC9 (Application-specific integrated circuit) -- Product development, VLSI Technology VSC10 (Application-specific integrated circuit) -- Product development, Semiconductor industry -- Product development, and Application-specific integrated circuits -- Product development
VSLI Technology announces two families of ASICs and outlines a product roadmap for 0.25 micron and below. The VSC9 and VSC10 product lines are manufactured on 0.25-micron and 0.20-micron processes, respectively. The families, which employ VLSI's trench architecture, will each have six layers of metal and a density of up to 18 million raw (14 million usable) gates. The families will be marketed in a standard cell format, which is becoming the format of choice among leading vendors. The VSC9 and VSC10 will be available for prototyping in summer 1997. Production of the VSC9 is scheduled to begin late in 1997, and the VSC10 will go into production in the quarter after the VSC9's production starts.
Electronic News (1991). April 1, 1996, Vol. 42 Issue 2110, p49, 1 p.
Cooperative agreement for product development, Integrated circuit fabrication, New technique, Programmable logic array, Application-Specific Integrated Circuit, Chip Express Corp. -- Product development -- 00231828, Seiko Epson Corp. -- Product development, Integrated circuit fabrication -- Innovations, Semiconductor industry -- Product development, Gate arrays -- Design and construction, and Application-specific integrated circuits -- Design and construction
Chip Express and Seiko-Epson sign a technology-transfer agreement under which laser ablation technology will be transferred from Chip Express to Seiko-Epson for high-volume gate array manufacturing and quick-turn prototyping of ASIC products. Chip Express intends to compete in the volume market and has signed on Seiko-Epson as an additional foundry partner as it prepares a new triple-layer metal (TLM) gate array architecture. Chip Express Pres Zvi Or-Bach says initial densities will be between 50,000 and 200,000 gates, and all products will have dedicated memory on top of the logic. The technology licensed to Seiko-Epson is used to remove metal from the interconnect layer in single- or double-metal layer systems to create 'opens'.