Kuehnert, Tom, Rusdorf, Stephan, and Brunnett, Guido
IEEE Computer Graphics and Applications. Sept-Oct, 2011, Vol. 31 Issue 5, p30, 13 p.
CAD/CAM/CIM system, 3D technology, Technology application, CAD-CAM systems -- Usage, Degrees of freedom (Mechanics) -- Analysis, Footwear industry -- Technology application, and Three-dimensional display systems -- Usage
Rapid Prototyping, Processor Architecture, Algorithm, Miniaturization, Reconfiguration, Circuit Design, Integrated circuit fabrication, Signal processing, Prototypes, Engineering -- Design and construction, Integrated circuit fabrication -- Testing, and Signal processing -- Research
Ageneralized architecture for signal processing, the wafer scale integration architecture for rapid prototyping (WARP), consists of the universal multiply-substract-add (UMSA) cell and the universal nonlinear (UNL) cell. The class of algorithms is broadened by the WARP architecture, using a single rapid-prototyping architecture. FIR filtering algorithms, FFT computation algorithms and L-U decomposition algorithms can be implemented. The high degree of regularity in signal processing algorithms makes them suitable for wafer scale integration (WSI). Mapping of the algorithm to an array of just a few types of cells on the wafer is facilitated. Careful test planning and strict adherence to design-for-test practices are important to testing WSI circuits. The UMSA and UNL cells are discussed in detail with the mapping of the FFT and L-U decomposition algorithms.