ELECTRONIC industries, MARKETS, INTEGRATED circuits, DEMAND (Economic theory), APPLICATION-specific integrated circuits, and FIELD programmable gate arrays
Reports developments in electronic industry as of 2004. Expected growth of the market for structure ASICS; Appearance of embedded processors on more FPGAS; Expectation of a growing demand for automated and accelerated analog circuit migration.
INTEGRATED circuits, AUTOMATION, ELECTRONICS, COMPUTER hardware description languages, and DESIGN
Reports developments related to electronic design automation. Tools to eliminate off-chip passives and the performance-draining characteristics for designers; Innovations in system-level design languages; Introduction of silicon virtual prototyping.
COST, INTEGRATED circuits, PROTOTYPES, INFORMATION technology, ECONOMICS, FIELD programmable gate arrays, PROGRAMMABLE logic devices, GATE array circuits, and ELECTRONIC circuits
The article provides information concerning the true cost of field-programmable gate array (FPGA) in the U.S. FPGAs make the ideal platform for prototyping most digital systems. Sometimes, FPGAs are available at a price point that makes sense in production volumes. However, there are compelling cases where FPGA prototypes must be converted to an application-specific integrated circuit (ASIC) for deployment. Looking at the economics, evidently free intellectual-property (IP) from a FPGA vendor can actually be very expensive.
HIGH technology industries, MANUFACTURES, SYSTEMS design, COMPUTERS, INTEGRATED circuits, ELECTRONICS, ELECTRONIC circuit design, SYSTEMS on a chip, and EMBEDDED computer systems
The article presents a forecast for EDA prototyping and implementation for 2006. It is expected that 2006's big push in the implementation flow will be toward tools and methodologies that maximize yield and manufacturability. Overall, the IC implementation market continues to expand. Design-for-manufacturability will no longer be a trendy buzzword and several new tools will perturb a design with the goal of improving its production yield. Manufacturers will begin to use technologies that can take in information about a design and use it to improve the design's parametric yield. True design-for-manufacturing (DFM) will emerge both for the SoC/digital design and custom/analog design environments. A comprehensive approach will be required as DFM, voltage drop, thermal issues, timing, low-power optimizations and signal integrity all intertwine. Ultimately, an integrated back-end platform will incorporate technologies that let designers anticipate the effect on chip layout of resolution enhancement technology.
INTEGRATED circuits, INFORMATION technology, INTEGRATED circuits industry, ELECTRONIC industries, FIELD programmable gate arrays, ELECTRONIC circuit design, APPLICATION-specific integrated circuits, and ELECTRONIC circuits
The article features Synplicity's Synplify Premier which comprises a pushbutton physical-synthesis flow that purports to remedy the difficulties in timing closure. It discusses the tool's ability to perform placement and routing simultaneously with all iterations done within a given run. The use of Synplicity's graph-based physical synthesis is also discussed. The article describes the tool's output. It also considers the advantages offered by the tool for designers prototyping application specific integrated circuits in field programmable gate arrays.
INTEGRATED circuits, COMPUTER architecture, COMPUTERS, MICROELECTRONICS, ELECTRONIC circuits, and REDUCED instruction set computers
This article discusses issues related to predictability in integrated circuits. In the summer of 2001, Atrenta arrived on the scene with tools based on what the company calls "predictive analysis" technology, which used rule checking to produce cleaner RTL. The tools comprise a unified physical planning, design, and implementation suite that spans from RTL design to initial placement. Architect provides system-on-a-chip architects with quick what-if feedback on the key physical tradeoffs of their block-level architectures. It takes in partial RTL, hard or soft IP, and/or chip specifications. Also, it lets users examine the impact of architectural decisions on a broad array of physical variables. Create uses physical synthesis to perform silicon virtual prototyping and floor-planning at RTL. Users can cross-probe between a timing report and their RTL code, locate and adjust problem areas, and incrementally recheck timing. Construct performs automatic floor-planning of designs with hundreds of mixed-size macro blocks and standard cells. It quickly generates routable floorplans.
INTEGRATED circuits, ENGINEERING design, INFORMATION technology, TECHNOLOGY, INTEGRATED circuit design, and ELECTRONICS
This article focuses on the First Encounter Global Physical Synthesis (GPS), a second-generation physical-synthesis tool crafted by Cadence by integrating silicon virtual prototyping and global physical synthesis on one environment. GPS lets designers create larger microchips than was practical in the past.