Hoey, Justin M., Reich, Michael T., Halvorsen, Aaron, Vaselaar, Dustin, Braaten, Kris, Maassel, Mike, Akhatov, Iskander S., Ghandour, Osman, Drzaic, Paul, and Schulz, Douglas L.
IEEE Transactions on Advanced Packaging. Nov2009, Vol. 32 Issue 4, p809-815. 7p. 4 Black and White Photographs, 4 Graphs.
RAPID prototyping, INTEGRATED circuits, RADIO frequency identification systems, RADIO antennas, ANTENNA design & construction, COPPER, and PROTOTYPE research
Optimization of radio-frequency identification (RFID) tags often requires several iterations of antenna design/fabrication/testing to meet cost and performance targets. The use of a rapid prototyping approach for antenna development would allow the designer an inexpensive and fast route to the refinement process. In this study, the performance of a commercial-off-the-shelf ultrahigh frequency (UHF) etched copper antenna was compared to printed silver antennas prepared by the following three direct-write techniques: maskless mesoscale materials deposition; matrix-assisted pulsed laser evaporation direct-write; and, collimated aerosol beam direct-write. The morphologies of the antennas were analyzed using contact and optical profilers with sheet resistance also being measured. operational characteristics were determined by mounting silicon integrated circuits (IC) to the four different types of antennas. The performance of tags that utilized direct-write silver antennas was comparable to the copper-based commercial tag. To our knowledge, this is the first demonstration where some of the direct-write rapid prototyping attributes (e.g., slight overspray, overlap of written lines, overall thickness less than 500 nm) are shown to not seriously impede RFID tag performance. These results demonstrate the utility of direct-write for rapid prototyping studies for UHF RFID antennas. [ABSTRACT FROM AUTHOR]
INTEGRATED circuits, PRINTED circuits industry, RAPID prototyping, MICROFABRICATION, ANTENNA radiation patterns, and MICROELECTROMECHANICAL systems
A stacked printed circuit board (PCB) approach for prototyping 3-D microfabrication enabled millimeter and submillimeter wave components and subsystems is proposed. To demonstrate this approach, a 4 to 8 GHz two element tapered slot antenna array with integrated rectangular coaxial 90^\circ hybrid, and its stand-alone elements, are designed and fabricated. Measured subsystem results show properly formed radiation patterns, realized gain from 9 to 11 dBi, and 3-dB beamwidth from 30^\circ to 45^\circ. Excellent agreement between simulations and measurements of individual components and the full subsystem as well as outcomes of a tolerance study and comparison to a Ka band micromachined subsystem confirm suitability of the proposed approach for fast, low-cost prototyping of 3-D micromachined rectangular coaxial components and subsystems. [ABSTRACT FROM AUTHOR]
RAPID prototyping, INTEGRATED circuits, and SWITCHING circuits
Presents a virtual prototyping method for the selection of the packaging and interconnection methods of a system. Overview of the prototyping method; Implementation of the models and methods in Java; Illustration of the method with the use of a case study of a satellite switch.
RAPID prototyping, INTEGRATED circuits, PRINTED circuits, ELECTRIC capacity, and COPPER
DON'T GET ME WRONG—I LOVE PRINTED CIRCUIT BOARDS. PCBs are, of course, essential in mass-produced products. Even for hobbyists, a small run assures almost perfectly repeatable circuits. And PCBs with a good ground plane are essential for high-frequency circuits operating at more than a few megahertz. A ground plane is a large area of copper that's used as a low-inductance electrical return path from components to a circuit's power supply. It prevents parasitic capacitance from smearing high-frequency signals into noise, and the absence of a ground plane is why you can't build a high-frequency circuit using a breadboard and expect it to work well, or at all. • But rapid prototyping with PCBs has drawbacks compared with the speed and ease of building a circuit on a breadboard. You can quickly make your own PCBs—as long as you don't mind the mess and some stained clothing and are willing to drill your own through holes. Or you can send your PCB layout to be made by a commercial service, but this takes several days at least and is more expensive. • So I began thinking about practical alternatives for high-frequency circuits that can provide maker-friendly prototypes that are fast to build, and easy to probe and alter. In this article, I'll be presenting one key idea; some follow-on strategies will appear on the IEEE Spectrum website in the coming weeks. I should say that I make no claims of originality: Indeed I employ some oft-forgotten, decades-old techniques, but they turn out to be surprisingly useful in an age of surface-mount components operating at gigahertz frequencies. [ABSTRACT FROM AUTHOR]
IEEE Transactions on Electron Devices. Nov2013, Vol. 60 Issue 11, p3842-3848. 7p.
PERFORMANCE evaluation, INTEGRATED circuits, SILICON, IMAGE converters, THREE-dimensional imaging, COMPLEMENTARY metal oxide semiconductors, and ANALOG-to-digital converters
We proposed a die-level 3-D integration technology for rapid prototyping of high-performance multifunctionality hetero-integrated systems. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die level. To realize the die-level 3-D integration, fine-sized backside through silicon via (TSV) and novel detachable technologies are developed. In this paper, we demonstrated a prototype 3-D stacked image sensor system using the die-level 3-D integration technology. Three different functional chips of CMOS image sensor, correlated double sampling, and analog-to-digital converter, which were fabricated by different technologies, were processed to form fine-sized backside Cu TSV of 5-\mum diameter and metal microbumps in die level. Each chip was sequentially stacked after evaluating the basic function to form a known-good-die 3-D stacked system. The fundamental characteristics of each functional chip were successfully evaluated in the fabricated prototype 3-D stacked image sensor system. [ABSTRACT FROM AUTHOR]
DATA mining, INTEGRATED circuits, COMPUTER programming, INTERNET protocols, SCHEME (Computer program language), and COMPLEMENTARY metal oxide semiconductors
This paper presents a programmable system-on-chip (SoC) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing a common SoC platform. In this implementation, an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed separately, the total area is approximately 143.03 \mm^2, while the area of the integrated platform is about 24.43 \mm^2. The area reduction is significant, so is the fabrication cost. Once the integrated platform chip is fabricated, three programming schemes are carried out to allow the integrated chip to act as the individual SoC design projects. A test chip is designed and implemented using the TSMC 0.13-\mu\m CMOS generic logic process technology. [ABSTRACT FROM AUTHOR]
INTEGRATED circuits, MICROELECTRONICS, EMBEDDED computer systems, ELECTRONIC circuits, TEMPERATURE measurements, HUMIDITY, DETECTORS, and MIXED signal circuits
This paper addresses the detection of hydrogen leaks for safety warning systems in automotive applications and the measurement of nitrogen oxide concentration in exhaust gases of zero-emission vehicles. The presented approach is based on the development of accurate models (including nonlinearity and error sources of real building components) for all the system elements: sensors and acquisition chain. This methodology enables efficient design space exploration and sensitivity analysis, allowing an optimal analog–digital and hardware–software partitioning. Such analysis drives also the development of effective data fusion techniques to reduce the measure uncertainty (due to cross-sensitivity to other gases or to temperature/humidity variations). Such techniques have been implemented on a microcontroller-based mixed-signal embedded platform for intelligent sensor interfacing with limited complexity, suitable for automotive applications. [ABSTRACT FROM AUTHOR]
SERVICE centers, INTEGRATED circuits, THREE-dimensional printing, CONDUCTING polymers, and ORGANIC conductors
Accucode 3D is to offer 3D printing of electronics for prototyping and low volume manufacture from locations in Colorado and Texas, writes Steve Bush. This is claimed to be the world's first service bureau for 3D printing of electronics, by Isreal-based Nano Dimension, which has provided the two DragonFly printers that Accucode will be using. Accucode 3D parent company Accucode also has a centre in Ireland, but without a DragonFly printer. [Extracted from the article]
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-silicon bugs, minimizing design risk and cost. The unique features of the approach include: 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; and 3) compensation of ac performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45 nm node that can map AMS modules across 22–90 nm technology nodes. A systematic emulation approach to map any analog transistor to 45 nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22 and 90 nm nodes with less than a 5% error. Several other 90 and 22 nm analog blocks are successfully emulated by the 45 nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H). [ABSTRACT FROM PUBLISHER]
Electronic Engineering Times (01921541). 7/16/2012, Issue 1625, p33-37. 4p.
INTEGRATED circuits, PROTOTYPES, REQUESTS for quotations, INTERNAL marketing, and METHODOLOGY
The article focuses on integrated circuit- (IC) package prototyping methodology which can offer cost estimates to fulfill a customer or internal marketing organization's request for quote (RFQ). It mentions that prototyping methodology must be easy to use, allow die prototyping, and should connect to downstream IC/package/board implementation tools. Moreover, the methodology allow optimization at both the die and system levels.
Cites the announcement by Giga Scale Integration Corp. of an alternative type of integrated circuit prototyping tool, InCyte. Design of the product to let users estimate and optimize design objectives including timing, area, power, leakage and yield; Possibility for InCyte to generate high-level floor plans fed into downstream implementation tools; Overview of the data that comes with the InCyte tool; Ability to create silicon virtual models for a given foundry and library.
PROTOTYPES, INTEGRATED circuits, WELDING, ELECTRONIC apparatus & appliances, RADIO frequency, and ELECTRICAL engineering
The article focuses on prototyping techniques. According to the article, this has become more difficult as the years pass. Tiny components and high-frequency circuits now demand rigorous prototyping methods. Prototyping requires a full complement of magnifiers, microscopes, lamps and tweezers. It also notes that one of the fastest ways to prototype a circuit is the dead bug technique. It uses a solid, copper-clad board as a ground plane. Meanwhile, a wire-tapped prototype is suitable for low-frequency designs. Another method is to use perforated board with solder pads or with both solder pads and plated-through holes.
This article describes the key process requirements for integrated circuit (IC) prototyping as well as its objectives and benefits for netlist and constraint handling, placement, power and signal routing, and analysis. The primary categories of chip-design specifications are based on functionality, timing, power and area. For a successful IC prototyping strategy, designers are required to start working early with design data, which may be incomplete or inaccurate. When placing IC prototypes, the objectives should center on the principal floor plan elements.
PROTOTYPES, INTEGRATED circuits, APPLICATION-specific integrated circuits, SYSTEMS on a chip, and EMBEDDED computer systems
This article focuses on prototyping application specific integrated circuits (ASIC) and systems on chips (SOC). Prototyping ASIC and SOC is essentially a step backward--turning an SOC into what some refer to half-jokingly as a system on board. In building a prototyping system, some designers reconstruct the functions of their ASIC using a mixture of discrete components, legacy ASIC, and FPGA providing new functions. The drawback of ASIC prototypes, however, is that they are harder to debug because it is difficult for designers to pinpoint the exact location of a bug on these systems. On the other hand, building a prototyping system from scratch is in some ways easier and in other ways harder to do than it was in the past.
INTEGRATED circuits, TEST methods, PRINTED circuits, SWITCHING circuits, ELECTRIC power, and INTEGRATED circuit interconnections
An electrical interconnect test method is proposed to detect and locate open defects occurring at interconnects between integrated circuits (ICs) and a printed circuit board. The test method does not utilize boundary scan flip-flops. It is based on a quiescent supply current that is made to flow through an interconnect under test by embedding a test circuit into the ICs. The circuit consists of MOS switches for each input pin of the ICs and its switch control circuit. SPICE simulations are used to examine whether open defects at the interconnects can be detected using this method. The simulation results indicate that the following defective interconnects are detected in addition to defective ones modeled as an open-circuit fault at a test speed of 25 MHz: defective interconnects modeled as a resistor of 150 $\Omega $ generating an additional propagation delay of 482 ps and as a capacitor of 4 pF generating an additional propagation delay of 128 ps and no logical changes. Testability of open defects using this test method is also examined experimentally by prototyping an IC in which the test circuit is embedded. The experiments indicate that a resistive interconnect of $150~\Omega $ and a defective one modeled as a capacitor of 2.2 nF can be detected by the test method at a test speed of 0.5 MHz. [ABSTRACT FROM AUTHOR]