UMAIR SAEED SOLANGI, TAYYAB DIN MEMON, ABDUL SATTAR NOONARI, and OMAIR AHMED ANSARI
Mehran University Research Journal of Engineering and Technology. Vol. 36 Issue 2, p343-352. 10 p.
Traffic Signal Control, State Flow, and Field Programmable Gate Array Prototyping
The problem of vehicular traffic congestion is a persistent constraint in the socio-economic development of Pakistan. This paper presents design and implementation of an intelligent traffic controller based on FPGA (Field Programmable Gate Array) to provide an efficient traffic management by optimizing functioning of traffic lights which will result in minimizing traffic congestion at intersections. The existent Traffic Signal system in Pakistan is fixed-time based and offers only Open Loop method for Traffic Control. The Intelligent Traffic Controller presented here uses feedback sensors to read the Traffic density present at a four way intersection to provide an efficient alternative for better supervisory Control of Traffic flow. The traffic density based control logic has been developed in a State Flow Chart for improved visualization of State Machine based operation, and implemented as a Subsystem in Simulink and transferred into VHDL (Hardware Description Language) code using HDL Coder for reducing development time and time to market, which are essential to capitalize Embedded Systems Market. The VHDL code is synthesized with Altera QUARTUS, simulated timing waveform is obtained to verify correctness of the algorithm for different Traffic Scenarios. For implementation purpose estimations were obtained for Cyclone-III and Stratix-III.
Chih-Chyau Yang, Chien-Ming Wu, and Chun-Ming Huang
Journal of Information Science and Engineering. Vol. 31 Issue 6, p1885-1901. 17 p.
3D prototyping platform, system-on-chip, SoC silicon prototyping, FPGA, and platform-based design
This paper presents a cost-effective three-dimensional (3D) SoC silicon prototyping platform, namely, MorPACK (morphing package). MorPACK is a 3D structure by stacking circuit substrates with high density connectors and has the capability of integrating heterogeneous blocks. Through system partitioning and tri-state interfaces, MorPACK allows a system to be easily extended by peripheral interfaces and improved by updating the bare dies/substrates. With these characteristics, total silicon prototyping cost of SoC projects/designs can be greatly reduced by utilizing the MorPACK common platform. In addition, compared to conventional substrates assembled with solder-balls and pogo-pin sockets, high density connectors in the MorPACK platform can also benefit the fabrication process with lower cost and higher yield rate. To demonstrate the effectiveness of the proposed methodology, an example of six SoC projects is implemented with MorPACK platform in this paper. The result shows that the fabrication cost can be significantly reduced by the proposed MorPACK platform, and the performance and power consumption of MorPACK in 3D can have good improvements than in 2D architecture.