The article discusses the methods to simplify the design and prototyping for large gate-count application-specific integrated circuits (ASICs). Topics discussed include prototyping by using a field-programmable gate array (FPGA) integrated circuit, challenges regarding the determination of the number and specifications of FPGAs and system memory based challenges. Topics including necessity for the prototype to meet timing requirements and addition of automation to the design are also discussed.
International Journal of Applied Electromagnetics & Mechanics; 2011, Vol. 36 Issue 1-2, p183-189, 7p, 3 Black and White Photographs, 3 Diagrams
HUMAN-computer interaction, APPLICATION software, COMPUTER interfaces, DEGREES of freedom, MICROPROCESSORS, MICROCONTROLLERS, INTERACTIVE computer systems, FIELD programmable gate arrays, and MOTION
A new kind of motion base is proposed for the purpose of setting up a user-friendly interaction system on a desktop. It aims at generating motion in various situations with a large range of movement using a simple mechanism, and generating motion adequate for an interaction with a man and for computer application. In this paper, a prototype of the motion base is developed. Its mechanism consists of a combination of a wheel drive locomotion mechanism and a 3-degrees of freedom (DOF) parallel link mechanism in parallel. It is aimed at generating 3 DOF translational motion on a desktop with a simple mechanism as a whole and with a large range of movement, especially in the horizontal direction. In consideration of application for man-computer interaction, the prototype is controlled by a microprocessor, a microcontroller and FPGA. This paper presents a description of the concept of the motion base for a desktop interaction system, the prototype mechanism, the control system and the preliminary experiment which demonstrates typical translational motions. [ABSTRACT FROM AUTHOR]
FIELD programmable gate arrays, PROTOTYPES, FIELD programmable gate arrays -- Design & construction, COMPUTER simulation, QUEUING theory, ARRAY processors, and COMPUTER network architectures
Emerging high-level hardware description and synthesis technologies in conjunction with field programmable gate arrays (FPGAs) have significantly lowered the threshold for hardware development. Opportunities exist to integrate these technologies into a tool for exploring and evaluating microarchitectural designs especially for newly proposed architectures. This paper presents a prototyping of a new processor core based on Queue architecture as starting point for application-specific processor design exploration. Using a hardware description language, we have created the Synthesizable model of a produced order parallel queue processor core for the integer subset parallel Queue architecture. A prototype implementation is produced by synthesizing the high-level model for the Stratix FPGA prototyping board. We show how to perform prototyping and optimizations to fully exploit the capabilities of the prototyped Queue processor core, while maintaining a common source base. [ABSTRACT FROM AUTHOR]
Electronics Systems & Software. Feb2006, Vol. 4 Issue 1, p36-41. 6p. 7 Color Photographs, 1 Diagram, 1 Chart.
Rapid prototyping, Computer software, Computer input-output equipment, Field programmable gate arrays, and Electronics engineers
Rapid prototyping systems based around field-programmable gate arrays (FPGAs) look as though they could provide a way of giving electronics engineers much quicker results than traditional methods. Using an FPGA as the platform for embedded design gave freedom to alter both hardware and software during development that couldn't have achieved using discrete fixed hardware. Using the tools, the author was able to work at a system level within the FPGA, providing a high level of interaction with the design hardware and software during development. This allowed developing and testing the design 'live', without the overhead involved in hardware simulation. [ABSTRACT FROM AUTHOR]
SYSTEMS on a chip, EMBEDDED computer systems, INTEGRATED circuits, and FIELD programmable gate arrays
The article evaluates several Prototype Ready interface cards including the SFP + GT Module used for Datacom Telcom applications; the SATA GT Module used on SATA HDD applications; the 3 Channel GMII PHY Interface Module from S2C Inc.
FIELD programmable gate arrays and APPLICATION-specific integrated circuits
The article presents information on the proFPGA product series including field programmable gate array (FPGA) modules for application-specific integrated circuits (ASIC) prototyping, real time system integration and pre-silicon software development, from Pro Design.
FIELD programmable gate arrays, ELECTRONIC apparatus & appliances, and APPLICATION-specific integrated circuits
Focuses on the upsurge in the use of field programmable gate arrays (FPGA) in electronic products. Availability of tools aimed at making it easier for traditional application specific integrated circuit designers to migrate to FPGA; Increased flexibility of FPGA; Advantages for engineers designing consumer-based end products containing one or more standards.
GEOMETRIC quantization, MATHEMATICAL optimization, FIELD programmable gate arrays, ARTIFICIAL neural networks, and RAPID prototyping
This paper presents an optimizing methodology for the implementation of a Learning Vector Quantization (LVQ) neural network in a Field Programmable Gate Array (FPGA) device. Starting from an algorithmic specification in the form of a Factorized and Conditioned Data Dependence Graph (GFCDD), we suggest a design methodology of the LVQ-dedicated architecture. This formal methodology is called AAA, “Algorithm Architecture Adequation”. Using graph transformations, it allows the generation of an optimized circuit implementation at the Register Transfer Level (RTL). It is associated to the SynDEx-IC software tool. Based on this formal methodology, we are able to explore and generate various LVQ network implementations by varying the LVQ sizes while minimizing the hardware resources and the design time. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized LVQ implementation was tried on two types of Virtex devices. [ABSTRACT FROM AUTHOR]
FIELD programmable gate arrays, ELECTRONIC systems, ELECTRONIC circuit design, PROGRAMMABLE logic devices, and GATE array circuits
This article reports that launched some two years ago, Emulation and Verification Engineering's (EVE) debut product, the ZeBu-ZV prototyping system was touted as a "personal emulator." It remains popular as a prototyping platform, offering the best features of emulator and field programmable gate arrays (FPGA)-based prototyping platforms in one product. Meanwhile, FPGA capacities, as well as system-on-achip (SoC) design sizes, have expanded. After about a year of development, larger FPGAs and SoC designs find their confluence in EVE's ZeBu-XL. The next-generation prototyping system has the capacity to handle very large SoC designs and offers a number of features that engender ease of use and flexibility in debugging. A number of factors contribute to ZeBu-XE's speed. First, there's the size of its Virtex II 8000 FPGAs, which holds down the number of FPGAs required to map a design. Emulators can have hundreds, if not thousands, of FPGAs on multiple boards interconnected by backplanes. ZeBu-XL is integrated with the most popular ASIC and FPGA synthesis tools and includes a complete compilation software suite.
FIELD programmable gate arrays, TELECOMMUNICATION, ELECTRIC power consumption, INTEGRATED circuits, and RAPID prototyping
In this article the author discusses the role of field programmable gate arrays (FPGAs) in telecommunication industry to reduce power consumption. He explains that FPGAs allow the equipment vendors to integrate several electronic components into a single integrated circuit (IC) thereby reducing the amount of heat that needs to be extracted. He informs that original equipment manufacturer (OEM's) are opting for FPGAs over ICs and it also offer flexibility and facilitate rapid prototyping.
FIELD programmable gate arrays, COMPUTER operating systems, PROGRAMMABLE logic devices, PROTOTYPES, and GATE array circuits
The article focuses on the prototype of field programmable gate arrays (FPGA). FPGA prototypes are mostly used as the project requires high speed and capacity during the integration stages. Since many unforeseen software bugs are related to the complexity of integrating operating system (OS), applications and hardware, an at-speed FPGA prototype allows for many extra months of rigorous software testing at the crucial integration stage.
Reports developments related to electronic design automation as of January 2003. Use of field programmable gate arrays on prototypes; Enhancement of diagonal interconnect routing; Function of the process simulation.
Electronics Weekly; 12/1/2004, Issue 2173, p31-31, 1/9p, 1 Color Photograph
SEMICONDUCTOR industry, FIELD programmable gate arrays, PRINTED circuits, COMPUTER storage device industry, and ELECTRONIC industries
This article reports that Lattice Semiconductor Corp. has announced two evaluation kits for its LatticeEC FPGAS. The Standard and Advanced Evaluation Platforms provide options for implementing system-level logic, memory functions and support for PCI, DDR, FCRAM and SPI4. Each kit has an FPGA PCB with a prototyping area, power regulation and interface connectors. The standard version is available with either the LFEC6E-4F484C or LFEC2OE-4F484C. an SPI flash memory for configuration, SMA pads for high-speed signals/clocks, a prototyping area and LEDs for visual feedback.
ELECTRONIC apparatus & appliances, PROTOTYPES, FIELD programmable gate arrays, ELECTRONICS, and ENGINEERING
Evaluates the ProASIC3 starter kit from Actel Corp. Availability of the kit in a prototyping and a low-cost evaluation version; Benefits of the starter kit; Inclusion of an A3P250 FPGA soldered directly to an evaluation board in the EVAL kit.
INTEGRATED circuit verification, FIELD programmable gate arrays, GATE array circuits, RAPID prototyping, INTELLECTUAL property, and ROUTING (Computer network management)
The article discusses the challenges to physical verification of a system-on-a-chip (SoC), functional verification trends in 2011, and issues on intellectual property (IP) integration. It states that the verification process requires rule checking integration with the chip's placement and routing. It says that virtual prototyping and field programmable gate arrays (FPGA)-based emulation and acceleration devices are expected to be adopted in 2011 aggravated by the desire to develop SoC.