Liu, F., Tan, Q., Chen, G., Song, X., Ait Mohamed, O., and Gu, M.
IET Computers & Digital Techniques. Jul2010, Vol. 4 Issue 4, p306-316. 11p. 9 Diagrams, 4 Graphs.
Algorithms, Field programmable gate arrays, Programmable logic devices, Gate array circuits, and Microprocessors
As an important part of many processors's floating point unit, fused multiply-add unit performs a multiplication followed immediately by an addition. In IBM POWER6 microprocessor's fused multiply-add unit, a fast 128-bit floating-point end-around-carry (EAC) adder is proposed. Very few algorithmic details exist in today's literature about this adder. In this study, a complete designed EAC adder that can work independently as a regular adder is proposed. Details about the proposed EAC adder's arithmetic algorithms are described. In IBM's original EAC adder, the Kogge–Stone tree has been chosen for its high performance on ASIC technology. In this study, the authors present a comparative study on different parallel prefix trees which are used in the design of our new EAC adder targeting field programmable gate array (FPGA) technology. Our study highlights the main performance differences among 14 different architecture configurations focusing on the area requirements and the critical path delay. The experimental results show that there is one architecture configuration with the lower area requirement and the higher performance. [ABSTRACT FROM AUTHOR]
VIDEO coding, DISCRETE cosine transforms, COMPLEMENTARY metal oxide semiconductors, RATE distortion theory, and ALGORITHMS
In High Efficiency Video Coding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high-throughput unified DCT/IDCT architectures. The proposed architectures can process variable DCT/IDCT block sizes according to the HEVC standard. The proposed architectures were prototyped on TSMC 65 nm CMOS technology. The prototyping results show that the two unified architectures have throughput of 15.24 and 16.03 Gsps, respectively, and they can encode video sequences with resolutions up to 8 K at 120 fps and decode the same resolution at 240 fps using only one circuit for both DCT and IDCT. [ABSTRACT FROM AUTHOR]
FALSE alarms, DETECTORS, RADAR, ALGORITHMS, ELECTROMAGNETISM, INTEGRATED circuits, DATA pipelining, PROBABILITY theory, and STATISTICS
The design and field programmable gate array (FPGA)-based realisation of automatic censored cell averaging (ACCA) constant false alarm rate (CFAR) detector based on ordered data variability (ODV) is discussed here. The ACCA–ODV CFAR algorithm has been recently proposed in the literature for detecting radar target in non-homogeneous background environments. The ACCA–ODV detector estimates the unknown background level by dynamically selecting a suitable set of ranked cells and doing successive hypothesis tests. The proposed detector does not require any prior information about the background environment. It uses the variability index statistic as a shape parameter to accept or reject the ordered cells under investigation. Recent advances in FPGA technology and availability of sophisticated design tools have made it possible to realise the computation intensive ACCA–ODV detector in hardware, in a cost-effective way. The architecture is modular and has been implemented and tested on an Altera Stratix II FPGA using Quartus II software. The post place and route result show that the proposed design can operate at 100 MHz, the maximum clock frequency of the prototyping board and for this frequency the total processing time required to perform a single run is 0.21 µs. This amounts to a speedup for the FPGA-based hardware implementation by a factor of ∼110 as compared to software-based implementation, which takes 23 µs to perform the same operation. [ABSTRACT FROM AUTHOR]
VERY large scale circuit integration, MPEG (Video coding standard), ALGORITHMS, INTEGRATED circuits, COMPLEMENTARY metal oxide semiconductors, and TRANSPUTERS
An efficient architecture with the fast algorithm for MPEG-4 shape coding is proposed. The authors apply the fast shape coding algorithm, with contour-based binary motion estimation (CBBME), which is based on the properties of a boundary mask. By using the block-matching motion estimation and the extended approach on centre-biased motion vector distribution with shrinking of the search range, a large number of search points in BME can be skipped. Based on this algorithm, a dedicated architecture design using the proposed CBBME algorithm is developed. With certain optimisation and design considerations, the memory access and processing cycles can be reduced. The average number of clock cycles for the processing of one binary alpha block is only 1708, which is only 56% of the previous design. In addition, a prototyping chip for shape coding is implemented and verified. The die area is 2.4×2.4 mm2 with TSMC 0.18 µm CMOS technology and the maximum clock frequency is 53 MHz. [ABSTRACT FROM AUTHOR]
IET Generation, Transmission & Distribution; Jan2007, Vol. 1 Issue 1, p1-7, 7p, 3 Black and White Photographs, 9 Diagrams, 1 Chart, 2 Graphs
ELECTRIC controllers, COMPUTER operating systems, ALGORITHMS, FEEDBACK (Electronics), and REAL-time computing
The paper describes the implementation of a centralised control-design scheme in a real-time laboratory-based dynamic simulator. A centralised multivariable-control algorithm is designed employing remote feedback signals considering delay in signal transmission. The transmitted signals can be used for multiple-swing-mode damping using a single controller. Such an algorithm is numerically intensive owing to the high controller size and the predictor that takes care of the delay in signal transmission. The performance of the proposed controller is demonstrated by practical implementation using a rapid-prototyping controller mounted on a PC-ATX. Results of the experimental tests are shown for a detailed model of the power system implemented using Linux PC-based multiprocessor technology. [ABSTRACT FROM AUTHOR]