Electronic News (1991). April 21, 1997, Vol. 43 Issue 2164, p50, 2 p.
Technology development, Programmable logic array, Performance improvement, and Programmable logic devices -- Development and progression
The design verification cycle is a critical part of the design process that must be examined before design reuse or programmable systems-on-a-chip become a normal part of high performance, high capacity programmable logic. The design verification cycle traditionally includes debugging, redesign steps and prototyping. A minimized design verification cycle is one advantage that separates standard-cell ASICs and gate arrays from programmable logic. The indeterminate nature of the programmable logic debugging process hinders compression. The two most commonly used approaches for finding design defects are the JTAG and SCAN methodologies. Design re-layout is another methodology, which is normally used for SRAM-based FPGA design.
Electronic News (1991). June 10, 1996, Vol. 42 Issue 2120, p48, 1 p.
Programmable logic array, Hardware product introduction, Actel Corp. -- Product introduction -- 00227218, Technical Data Freeway Inc. -- Contracts -- 00359248, Actel A32200DX (Programmable logic array) -- Product introduction, Integrated circuits -- Product introduction, and Semiconductor industry -- Product introduction
Actel announces the A32200DX FPGA at the same time it reveals it has an intellectual property agreement with Technical Data Freeway (TDF). The agreement lets FPGA developers select from 90 different TDF cores for use in Actel devices. The accord allows OEMs to merge predefined functions optimized for high-performance applications with customized logic. For TDF, the deal allows the company's designs to gain entry into the low volume and prototyping markets. Actel A32200DX is a 20,000-gate device, and the company claims it is the first antifuse FPGA to have dual-port, on-chip SRAM. Although the SRAM does not make it possible to reprogram the A32200DX, the on-chip SRAM will be employed for high-speed RAM functions. The FPGA operates at 100MHz, allowing data to travel rapidly through out the entire system, not just the core. The A32200DX ships in Jun 1996 and costs $225 in sets of 5,000.
Electronic News (1991). April 1, 1996, Vol. 42 Issue 2110, p49, 1 p.
Cooperative agreement for product development, Integrated circuit fabrication, New technique, Programmable logic array, Application-Specific Integrated Circuit, Chip Express Corp. -- Product development -- 00231828, Seiko Epson Corp. -- Product development, Integrated circuit fabrication -- Innovations, Semiconductor industry -- Product development, Gate arrays -- Design and construction, and Application-specific integrated circuits -- Design and construction
Chip Express and Seiko-Epson sign a technology-transfer agreement under which laser ablation technology will be transferred from Chip Express to Seiko-Epson for high-volume gate array manufacturing and quick-turn prototyping of ASIC products. Chip Express intends to compete in the volume market and has signed on Seiko-Epson as an additional foundry partner as it prepares a new triple-layer metal (TLM) gate array architecture. Chip Express Pres Zvi Or-Bach says initial densities will be between 50,000 and 200,000 gates, and all products will have dedicated memory on top of the logic. The technology licensed to Seiko-Epson is used to remove metal from the interconnect layer in single- or double-metal layer systems to create 'opens'.