- Book
- 1 online resource (xvi, 542 p.) : ill.
- Book
- xvi, 542 p. : ill. ; 24 cm. + 1 CD-ROM (4 3/4 in.)
- Introductio; Fundamental Concepts; The Origin of FPGAs; Alternative FPGA Architectures; Programming (Configuring) an FPGA; Who Are All the Players?; FPGA Versus ASIC; HDL-Based Design Flows; Silicon Virtual Prototyping; C/C++ etc.Based Design Flows;
- DSP-Based Design Flows; Embedded Processor-Based; Modular and Incremental Design; High-Speed Design and Other PCB Considerations; Observing Internal Nodes in an FPGA; Intellectual Property; Migrating ASIC Designs to FPGAs and Vice Versa; Simulation, Synthesis, Verification, etc.; Choosing the Right Device; Gigabit Transceivers; Reconfigurable Computing; Creating an Open-Source-Based
- Design Flow; Future FPGA Developments; Appendix A:
- Signal Integrity 101; Capacitive and inductive coupling(crosstalk), Chip-level effects, Board-level effects, The evolution of delay specifications; Appendix B: Deep-Submicron Delay Effects 101, A potpourri of definitions, Alternative interconnect models, DSM delay effects
- Summary, The Ouroboras, Many-to-one implementations; Appendix C: Linear Feedback Shift Registers 101, More taps than you know what to do with, Seeding an LFSR, FIFO applications, Modifying LFSRs to sequence 2n values, Accessing the previous value, Encryption and decryption applications,
- Cyclic redundancy check applications.
- Introductio; Fundamental Concepts; The Origin of FPGAs; Alternative FPGA Architectures; Programming (Configuring) an FPGA; Who Are All the Players?; FPGA Versus ASIC; HDL-Based Design Flows; Silicon Virtual Prototyping; C/C++ etc.Based Design Flows;
- DSP-Based Design Flows; Embedded Processor-Based; Modular and Incremental Design; High-Speed Design and Other PCB Considerations; Observing Internal Nodes in an FPGA; Intellectual Property; Migrating ASIC Designs to FPGAs and Vice Versa; Simulation, Synthesis, Verification, etc.; Choosing the Right Device; Gigabit Transceivers; Reconfigurable Computing; Creating an Open-Source-Based
- Design Flow; Future FPGA Developments; Appendix A:
- Signal Integrity 101; Capacitive and inductive coupling(crosstalk), Chip-level effects, Board-level effects, The evolution of delay specifications; Appendix B: Deep-Submicron Delay Effects 101, A potpourri of definitions, Alternative interconnect models, DSM delay effects
- Summary, The Ouroboras, Many-to-one implementations; Appendix C: Linear Feedback Shift Registers 101, More taps than you know what to do with, Seeding an LFSR, FIFO applications, Modifying LFSRs to sequence 2n values, Accessing the previous value, Encryption and decryption applications,
- Cyclic redundancy check applications.
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- Book
- xvi, 542 p. : ill. ; 24 cm
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