Submitted to the Department of Electrical Engineering.
Thesis (Ph.D.)--Stanford University, 2012.
High-performance continuous-time sigma-delta modulators that utilize rectangular DAC feedback pulses suffer from a relatively high sensitivity to timing jitter. In order to overcome this problem, many state-of-the-art designs rely on SC feedback pulses. Unfortunately, the large peak currents generated by the SC waveform dictate higher power dissipation, primarily due to the increased slew rate requirements in the active RC circuit that is typically employed as the modulator's first integrator. This research reports on a proof-of-concept evaluation of an alternative jitter-insensitive approach that replaces the slew-rate limited active RC circuit with a low-power Gm-C integrator that can efficiently absorb SC feedback waveforms. To further reduce the requirements on the Gm-C circuit in terms of linearity, we employ a polynomial-based digital-domain nonlinearity compensation. The required coefficients are background calibrated using a highly linear, but low SNR auxiliary modulator. In this scheme, the estimates of the linearization coefficients are obtained by minimizing the mean squared error between the two outputs using an LMS algorithm. A 65-nm CMOS experimental prototype achieves 79 dB dynamic range, 74.3 dB peak SNR and 73.3 dB peak SNDR for a signal bandwidth of 1.95 MHz and 124.8 MHz sampling rate. The IC dissipates 8.55 mW from a 2.5 V supply.