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Dynamic amplifiers for high-speed pipelined A/D conversion [electronic resource] / Luan Ray Nguyen.

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Author/Creator:
Nguyen, Luan Minh.
Language:
English.
Publication date:
2012
Imprint:
2012.
Format:
  • Book, Thesis
  • 1 online resource.
Note:
Submitted to the Department of Electrical Engineering.
Note:
Thesis (Ph.D.)--Stanford University, 2012.
Summary:
Analog-to-digital converters (ADC) are a vital part of a many applications that require an interface with real-world analog signals. Fueled by the ever increasing demand for higher bandwidth and lower power consumption in many areas, the energy efficiency of ADCs becomes a critical performance criterion. Today, there exist a variety of ADCs that provide high energy efficiency solutions only for low bandwidths (below ~100 MHz). In the high-speed space (above 100 MHz), however, the energy efficiency of ADCs degrades dramatically, and this is especially visible for pipelined ADCs, which take 3-5 times more energy than other architectures that do not emphasize high speed. Furthermore, existing non-pipelined solutions for this bandwidth range are few in numbers, and this presents an opportunity for innovation at both the architectural and circuit design level. This thesis explores a pipelined ADC design that employs a variety of low-power techniques such as dynamic residue amplification and incomplete settling in a unique way to maximize the speed while maintaining low energy (98 fJ/conv-step). The resulting work advances the state-of-the-art by simultaneously achieving a high conversion rate (500 MS/s), low power (5.1 mW), moderate resolution (8 bits), and low input capacitance (55 fF). The experimental converter was implemented in a 65-nm Silicon-on-Insulator (SOI) CMOS process and is among the first high-performance ADCs employing this technology.
Contributor:
Murmann, Boris, primary advisor.
Horowitz, Mark (Mark Alan), advisor.
Wooley, Bruce A., 1943- advisor.
Stanford University. Department of Electrical Engineering

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