Submitted to the Department of Electrical Engineering.
Thesis (Ph.D.)--Stanford University, 2013.
Advanced wireless technologies, such as LTE and LTE advanced, require low-power, high-speed, and high-resolution analog-to-digital converters (ADCs). At present, only the pipelined ADC architecture is capable of meeting the stringent bandwidth, linearity, and resolution requirements for this application. However, in current products, the power efficiency of this architecture is limited by the use of operational amplifiers as inter-stage gain elements. This research investigates an approach where the critical operational amplifiers are replaced by a pulsed-based bucket brigade amplifier, which achieves voltage gain by redistributing charge form a large sampling capacitor to a small load capacitor. This circuit performs the residue amplification with lower power, but is weakly nonlinear and therefore requires digital linearization. Since the power overhead for digital arithmetic in modern CMOS technologies is low, this approach has the potential to yield large overall power savings. To evaluate this concept, a prototype ADC was implemented in 65-nm CMOS. The converter operates at 200 MS/s, consumes 11.5 mW from a 1-V supply, and occupies 0.26 mm2. It achieves an SNDR of 65 dB at low input frequencies and 57.6 dB near Nyquist, which corresponds to an SNDR-based Schreier FOM of 164.5 dB and 157 dB, respectively. These results validate the concept of the proposed pulse-based bucket brigade amplification, and the achieved performance compares favorably with the state of the art.