Calibration ADC and algorithm for adaptive predistortion of high-speed DACs [electronic resource]
- Dastgheib, Alireza.
- Physical description
- 1 online resource.
All materials are stored offsite. Request items 2 business days in advance. Maximum 5 items per day.
University Archives: request at Special Collections service desk
3781 2013 D
- In-library use 3781 2013 D
- Murmann, Boris, primary advisor.
- Poon, Ada Shuk Yan Poon, advisor.
- Wooley, Bruce A., 1943- advisor.
- Stanford University. Department of Electrical Engineering.
- In this thesis, the design and implementation of circuits and signal processing algorithms required for digital predistortion of a digital-to-analog converter (DAC) with an open-loop driver is presented. On the circuit design side, the implementation of a high precision, high acquisition-bandwidth calibration analog-to-digital converter (ADC) for sampling the DAC output is discussed. The ADC has a cyclic core and a variant of the switched-RC sampling network suitable for high frequency operation. It is implemented in 90-nm CMOS and achieves an SFDR of higher than 72 dB for input frequencies under 500 MHz. On the signal processing side, a calibration algorithm is presented that uses the input/output data of the DAC to identify its nonlinearity and cancel it through digital predistortion. The algorithm represents a novel technique for the linearization of Hammerstein systems with low computational cost and is suitable for hardware realization. Overall, this calibration architecture improves the SFDR of the DAC by close to 30 dB to achieve a final linearity of 53 dB for input frequencies up to 400 MHz and peak-to-peak differential output swing of 800 mV.
- Publication date
- Alireza Dastgheib.
- Submitted to the Department of Electrical Engineering.
- Thesis (Ph.D.)--Stanford University, 2013.